Abstract
The present endeavor attempts to develop an explicit threshold voltage model of linearly graded work function engineered Silicon-On-Insulator MOSFET considering the effects of localized charges trapped at front high-k gate stack/channel and buried oxide layer/channel interfaces. As the accumulation of such equivalent oxide charges modulate the flat band voltage and alter the threshold voltage characteristics of the device, the inclusion of such effects is inexorable while formulating its analytical model. Hence, analytical methodology based extensive study of the potential distribution and threshold voltage behavior of the device affected by positive/negative trapped charges is demonstrated here by varying the channel thickness, high-k dielectrics and drain bias with subsequent comparison with a fresh SOI MOSFET equivalent. All analytical corollaries are compared with relevant ATLAS simulated data to corroborate the eminence of the derived model.
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Acknowledgements
Priyanka Saha thankfully acknowledges this publication as an outcome of the R&D work undertaken project under the Visvesvaraya PhD Scheme of Ministry of Electronics & Information Technology, Government of India, being implemented by Digital India Corporation.
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Saha, P., Banerjee, P., Dash, D.K. et al. Interface Trap Charge Induced Threshold Voltage Modeling of WFE High-K SOI MOSFET. Silicon 12, 2893–2900 (2020). https://doi.org/10.1007/s12633-020-00386-5
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DOI: https://doi.org/10.1007/s12633-020-00386-5