Design and Analysis of a Field Plate Engineered High Electron Mobility Transistor for Enhanced Performance

Abstract

In this paper, the impact of drain drift region and vertical scaling on breakdown performance is investigated through exhaustive technology computer-aided design simulations. The breakdown behavior for drain-connected, gate-connected and dual field plate designs is explored and the physical insights were developed by studying their electric field and potential profile intricacies. Useful optimization laws are unraveled, and by this, breakdown voltage is pushed to higher limits by engineering the gallium nitride (GaN) buffer thickness, drain drift region and field plate length. A thicker GaN buffer with a field plate and larger drain drift region improve the breakdown voltage to maximum values by mitigating punch through and impact ionization mechanisms of performance degradation. The proposed dual field plate combines the merits of using thicker buffer, extended gate drain drift region and both field plates emerging as the optimized design. The breakdown limiting peak electric field is mitigated in dual field plate designs enhancing its breakdown voltage 1.4 to 1.7 times that of a conventional high electron mobility transistor without field plate. Finally, the input and output characteristics are also depicted along with the frequency response. These results demonstrate the efficacy of field plates in reducing and redistributing the critical peak electric fields and thicker GaN buffer giving further cushion to push the breakdown voltage to higher values by negotiating vertical effects such as punch through and lends design guidelines for further improvements.