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Investigation of Various Bumps and Redistribution Lines to Inhibit Protected Silicon Nitride Cracks in High Pattern Density Chip Package

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Abstract

Mechanical stress related to chip packaging failure is the most common reliability issue in semiconductor devices, especially for high pattern density of very-large-scale integration. In this paper, redistribution lines (RDL) corresponding to gold and copper materials with capped layers (Sn-Ag and Au-Ni) were evaluated to investigate the structure dependency on the mechanical properties of intermetallic compounds, and to provide a solution to improve chip package reliability in regard to protect Si3N4 cracks. The simulation results revealed that a thicker Si3N4 film combined with the corner rounding of bump/RDL structures could mitigate Si3N4 film cracks. Voids induced by the fine pitch configuration of the top Al increase the potential risk of Si3N4 cracks during chip packaging. The reflow temperature is a major factor increasing the thermal stress in RDL patterns rather than from the bump structure. A high temperature storage test applied to the Cu pillar/Sn-Ag capping was used to investigate the intermetallic compound growth, shear strength, and hardness.

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Authors and Affiliations

  1. Department of Mechanical Engineering, National Cheng-Kung University, No. 1, University Road, Tainan City, 701, Taiwan

    Ching-Yuan Ho, Yuan-Chih Chang & Hwa-Teng Lee

  2. Department of Mechanical Engineering, Chung Yuan Christian University, No. 200, Chungpei road, Chung-Li District, Taoyuan City, 302, Taiwan

    Hsin Cheng

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  1. Ching-Yuan Ho
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  2. Hsin Cheng
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  3. Yuan-Chih Chang
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  4. Hwa-Teng Lee
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Correspondence to Ching-Yuan Ho.

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Ho, CY., Cheng, H., Chang, YC. et al. Investigation of Various Bumps and Redistribution Lines to Inhibit Protected Silicon Nitride Cracks in High Pattern Density Chip Package. J. Electron. Mater. 49, 5613–5621 (2020). https://doi.org/10.1007/s11664-020-08310-8

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  • DOI: https://doi.org/10.1007/s11664-020-08310-8

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