Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process

Abstract

This work presents the design of a novel static-triggered power-rail electrostatic discharge (ESD) clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit (TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current (I _leak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.

创新点

基于静态探测机制相对于瞬态探测机制在瞬态噪声性能上的优势, 本文提出了一种新型的静态触发型电源钳位ESD保护电路。通过有效的触发电路设计, 本文提出的新型保护电路能在ESD情况下相对于传统静态触发电路实现最好的泄放性能, 同时, 在正常操作情况下消耗最小的泄漏电流。本文提出的电路在65纳米CMOS工艺下得到了验证, 测试结果表明:本文提出的电路对与ESD事件一样快速的瞬态噪声具有免疫力, 同时, 本文提出的电路能为65纳米的CMOS工艺提供有效的片上ESD防护方案。