Abstract
A new power-rail electrostatic discharge (ESD) clamp circuit with ultra low leakage current and adjustable holding voltage, composed of an NMOS ESD clamp device and a new ESD detection circuit, is proposed in this chapter. The new ESD detection circuit has been verified in a 65-nm CMOS process. Simulating results show that the novel circuit has a standby leakage current of only 20.85 nA, which is two-orders lower than that of the traditional design. Also, by modifying the number of diodes in the circuit, we can adjust the holding voltage of the proposed ESD clamp circuit conveniently to achieve better immunity against mistrigger and transient-induced latch-on events.
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References
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Acknowledgment
This work is supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No 2009ZX02305), the Young Scientists Fund of the National Natural Science Foundation of China (Grant No 61106101), and the National Science Fund for Distinguished Young Scholars of China (Grant No 60925015).
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Zhang, X., Wang, Y., Lu, G., Jia, S., Zhang, X. (2014). A Low Leakage Power-Rail ESD Clamp Circuit with Adjustable Holding Voltage in Nanoscale Process. In: Xing, S., Chen, S., Wei, Z., Xia, J. (eds) Unifying Electrical Engineering and Electronics Engineering. Lecture Notes in Electrical Engineering, vol 238. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4981-2_188
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DOI: https://doi.org/10.1007/978-1-4614-4981-2_188
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