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Cost-effective synthesis of QCA logic circuit using genetic algorithm

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Abstract

Quantum-dot cellular automata (QCA) is a field coupling nano-technology that has drawn significant attention for its low power consumption, low area overhead, and achieving a high speed over the CMOS technology. Majority Voter (MV) and QCA Inverter (INV) are the primitive logic in QCA for implementing any QCA circuit. The performance and cost of a QCA circuit directly depend on the number of QCA primitives and their interconnections. Their optimization plays a crucial role in optimizing the QCA logic circuit synthesis. None of the previous works considered elitism in GA, all the optimization objectives (MV, INV and Level), and the redundancy elimination approach. These profound issues lead us to propose a new methodology based on Genetic algorithm (GA) for the cost-effective synthesis of the QCA circuit of the multi-output boolean functions with an arbitrary number of inputs. The proposed method reduces the delay and gate count, where the worst-case delay is minimized in terms of the level. This methodology adapts elitism to preserve the best solutions throughout the intermediate generations. Here, MV, INV, and levels are optimized according to their relative cost factor in a QCA circuit. Moreover, new methodologies are proposed to create the initial population, maintain the variations, and eliminate redundant gates. Simulation results endorse the superiority of the proposed method.

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Data Availability

The authors declare that the data supporting the findings of this study are available within the article.

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Acknowledgements

This work is sponsored by the Young Faculty Research Fellowship (YFRF) of Visvesvaraya Ph.D. scheme through the grant number MLA/MUM/GA/ 10(37)B.

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Authors and Affiliations

  1. Department of CSE, Dumka Engineering College, Dumka, Jharkhand, India

    Amit Kumar Pramanik

  2. Department of CSE, NIT Durgapur, Durgapur, West Bengal, India

    Mahabub Hasan Mahalat & Bibhash Sen

  3. Department of IT, Tripura University, Suryamaninagar, India

    Jayanta Pal

  4. Department of Computer Engineering, Faculty of Engineering and Natural Sciences, Kadir Has University, Istanbul, Turkey

    Seyed-Sajad Ahmadpour

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  1. Amit Kumar Pramanik
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  2. Mahabub Hasan Mahalat
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  4. Seyed-Sajad Ahmadpour
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Correspondence to Seyed-Sajad Ahmadpour.

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Pramanik, A.K., Mahalat, M.H., Pal, J. et al. Cost-effective synthesis of QCA logic circuit using genetic algorithm. J Supercomput 79, 3850–3877 (2023). https://doi.org/10.1007/s11227-022-04757-0

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