The experimental data on the plasma etching of Si3N4 for sub-100 nm gate fabrication for high electron mobility transistors (HEMTs) based on InAlN/GaN heterostructures are analyzed. The influence of the plasma etching process parameters on the plasma-induced damage to the InAlN/GaN heterostructure is considered. The possibility of formation of a 70 nm-length gate InAlN/GaN HEMT using low damage reactive ion etching of Si3N4 is demonstrated.
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Translated from Izvestiya Vysshikh Uchebnykh Zavedenii, Fizika, No. 1, pp. 84–87, January, 2020.
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Filippov, I.A., Shakhnov, V.A., Velikovskii, L.E. et al. Plasma Etching in InAlN/GaN Hemt Technology. Russ Phys J 63, 94–98 (2020). https://doi.org/10.1007/s11182-020-02006-6
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DOI: https://doi.org/10.1007/s11182-020-02006-6