Abstract
Tunnel field effect transistors (TFETs) have proved themselves as a better choice for the replacement of MOSFET due to provision of scalability and possibility of better realization of goal to achieve subthreshold swing less than 60 mV/decade. Challenge of lower ON current in conventional TFET has been overcome by a heterojunction double-gate (DG) TFET structure in which a low bandgap material, magnesium silicide (Mg2Si) is implemented as source region. There is dire need to determine the reliability of such device under various constraints to optimize them for low-power and high-speed applications. Therefore, in this paper, authors examine the device reliability by investigating the analog/RF performance of Mg2Si source heterojunction double-gate TFET (MSH-DG-TFET) under the influence of interface trap charge polarity and density. This reliability analysis is accomplished by including the effect of trap charges (both positive interface charges, i.e., donors and negative interface charges, i.e., acceptors) at Si/SiO2 interface. Presence of these trapped acceptor and donor charges at Si/SiO2 interface modifies the flat-band voltage which in turn alters the performance of the device. It is revealed that for positive trap charge density of 1 × 1012 cm−2, the leakage current or off-state current of MSH-DG-TFET drastically increases from an order of 10–18 to 10–14 A/µm, thus degrading the performance. Further, presence of negative trap charges at interface tends to enhance the flat-band voltage that translates to the higher gate bias to turn the device ON. Results reveal that impact of positive interface charges is more pernicious on the device performance as compared to the negative interface charges. Thus, MSH-DG-TFET is susceptible to the donor traps existing at Si/SiO2 in comparison with the acceptor traps. Studies carried out may prove to be very useful for future research work in suggesting better TFET structures comprising of Mg2Si as source.
Similar content being viewed by others
References:
W.F. Brinkman, D.E. Haggan, W.W. Troutman, A history of the invention of the transistor and where it will lead us. IEEE J. Solid-State Circuits 32(12), 1858–1865 (1997). https://doi.org/10.1109/4.643644
A. Chaudhry, M.J. Kumar, Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review. IEEE Trans. Device Mater. Reliab. 4(1), 99–109 (2004). https://doi.org/10.1109/TDMR.2004.824359
G. Baccarani, M.R. Wordeman, R.H. Dennard, Generalized scaling theory and its application to a ¼ micrometer MOSFET design. IEEE Trans. Electron Devices 31(4), 452–462 (1984). https://doi.org/10.1109/T-ED.1984.21550
J. Appenzeller, Y.M. Lin, J. Knoch, P. Avouris, Band-to-band tunneling in carbon nanotube field-effect transistors. Phys. Rev. Lett. 93(19), 196805 (2004). https://doi.org/10.1103/PhysRevLett.93.196805
A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479(7373), 329–337 (2011). https://doi.org/10.1038/nature10679
K. Boucart, A.M. Ionescu, Double-gate tunnel FET with high-k gate dielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007). https://doi.org/10.1109/TED.2007.899389
B.V. Chandan, S. Dasari, K. Nigam, S. Yadav, S. Pandey, D. Sharma, Impact of gate material engineering on ED-TFET for improving DC/analogue-RF/linearity performances. Micro Nano Lett. 13(12), 1653–1656 (2018). https://doi.org/10.1049/mnl.2018.5131
S. Chander, B. Bhowmick, S. Baishya, Heterojunction fully depleted SOI-TFET with oxide/source overlap. Superlattices Microstruct. 86, 43–50 (2015). https://doi.org/10.1016/j.spmi.2015.07.030
S.S. Chauhan, A new design approach to improve DC, analog/RF and linearity metrics of Vertical TFET for RFIC design. Superlattices Microstruct. 122, 286–295 (2018). https://doi.org/10.1016/j.spmi.2018.07.036
J. Madan, S.S. Bisht, R. Chaujar, Heterojunction DG-TFET-Analysis of Different Source Material for Improved Intermodulation, IEEE 2nd International Conference on Trends in Electronics and Informatics (ICOEI), pp. 1080–1084, (2018). https://doi.org/10.1109/ICOEI.2018.8553856
B.R. Raad, S. Tirkey, D. Sharma, P. Kondekar, A new design approach of dopingless tunnel FET for enhancement of device characteristics. IEEE Trans. Electron Devices 64(4), 1830–1836 (2017). https://doi.org/10.1109/TED.2017.2672640
S. Shekhar, J. Madan, R. Chaujar, Source/gate material-engineered double gate TFET for improved RF and linearity performance: a numerical simulation. Appl. Phys. A 124(11), 739 (2018). https://doi.org/10.1007/s00339-018-2158-4
G. Kim, J. Lee, J.H. Kim, S.J.M. Kim, High on-current Ge-channel heterojunction tunnel field-effect transistor using direct band-to-band tunneling. Micromachines 10(2), 77 (2019). https://doi.org/10.3390/mi10020077
H.B. Joseph, S.K. Singh, R. Hariharan, P.A. Priya, N.M. Kumar, D.J. Thiruvadigal, Hetero structure PNPN tunnel FET: analysis of scaling effects on counter doping. Appl. Surf. Sci. 449, 823–828 (2018). https://doi.org/10.1016/j.apsusc.2018.01.274
Z. Ahangari, Design and analysis of energy efficient semi-junctionless n+ n+ p heterojunction p-channel tunnel field effect transistor. J. Mater. Res. Express 6(6), 065901 (2019)
Y. Wu, H. Hasegawa, K. Kakushima, K. Ohmori, H. Wakabayashi, K. Tsutsui, A. Nishiyama, N. Sugii, Y. Kataoka, K. Natori, K. Yamada, Influence of Band Discontinuities at Source-Channel contact in Tunnel FET Performance, In Proceedings of 2013 International Workshop on Dielectric Thin Films, Tokyo, (2000). Corpus ID: 56228132. http://www.iwailab.ep.titech.ac.jp/pdf/201311iwdtf/wu.pdf
Y. Wu, H. Hasegawa, K. Kakushima, K. Ohmori, T. Watanabe, A. Nishiyama, N. Sugii, H. Wakabayashi, K. Tsutsui, Y. Kataoka, K. Natori, A novel hetero-junction tunnel-FET using semiconducting silicide–silicon contact and its scalability. Microelectron. Reliab. 54(5), 899–904 (2014). https://doi.org/10.1016/j.microrel.2014.01.023
M. Elnaggar, A. Shaker, M. Fedawy, A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps. Semicond. Sci. Technol. 34(4), 045015 (2019). https://doi.org/10.1088/1361-6641/ab0922
J. Madan, M. Dassi, R. Pandey, R. Chaujar, R. Sharma, Numerical analysis of Mg2Si/Si heterojunction DG-TFET for low power/high performance applications: impact of non-idealities. Superlattices Microstruct. 139, 106397 (2020). https://doi.org/10.1016/j.spmi.2020.106397
M. Dassi, J. Madan, R. Pandey, R. Sharma, A novel source material-engineered DG-TFET structure for RFIC applications. Semicond. Sci. Technol. 35(10), 105013 (2020). https://doi.org/10.1088/1361-6641/abaa5b
M. Dassi, J. Madan, R. Pandey, R. Sharma, Effect of temperature on analog performance of Mg2Si source heterojunction double gate tunnel field effect transistor. Mater. Today: Proc. (2020). https://doi.org/10.1016/j.matpr.2020.04.834
K. Ganapathi, Y. Yoon, S. Salahuddin, Analysis of InAs vertical and lateral band-to-band tunneling transistors: leveraging vertical tunneling for improved performance. Appl. Phys. Lett. 97(3), 033504 (2010). https://doi.org/10.1063/1.3466908
R. Jhaveri, V. Nagavarapu, J.C. Woo, Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans. Electron Devices 58(1), 80–86 (2010). https://doi.org/10.1109/TED.2010.2089525
J. Madan, R. Chaujar, Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability. IEEE Trans. Device Mater. Reliab. 16(2), 227–234 (2016). https://doi.org/10.1109/TDMR.2016.2564448
U.E. Avci, B.C. Kung, A. Agrawal, G. Dewey, V. Le, R. Rios, D.H. Morris, Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET, In 2015 IEEE International Electron Devices Meeting (IEDM), pp. 34–5, 2015. https://doi.org/10.1109/IEDM.2015.7409 828
A.S. Verhulst, D. Verreck, Q. Smets, K.H. Kao, M. Van de Put, R. Rooyackers, B. Soree, A. Vandooren, K. De Meyer, G. Groeseneken, and M. M. Heyns, Perspective of tunnel-FET for future low-power technology nodes, IEEE International Electron Devices Meeting, pp. 30–2. 4, 2014. https://doi.org/10.1109/IEDM. 2014.7047140
J. Madan, R. Pandey, R. Sharma, R. Chaujar, Investigation of electrical/analog performance and reliability of gate metal and source pocket engineered DG-TFET. Microsyst. Technol. (2020). https://doi.org/10.1007/s00542-020-04845-2
E. Duval, E. Lheurette, Characterisation of charge trapping at the Si–SiO2 (100) interface using high-temperature conductance spectroscopy. Microelectron. Eng. 65(1–2), 103–112 (2003). https://doi.org/10.1016/S0167-9317(02)00732-3
W. Cao, C. Yao, G. Jiao, D. Huang, H. Yu, M.F. Li, Improvement in reliability of tunneling field-effect transistor with pnin structure. IEEE Trans. Electron Devices 58(7), 2122–2126 (2011). https://doi.org/10.1109/TED.2011.2144987
X.Y. Huang, G.F. Jiao, W. Cao, D. Huang, H.Y. Yu, Z.X. Chen, N. Singh, G.Q. Lo, D.L. Kwong, M.-F. Li, Effect of interface traps and oxide charge on drain current degradation in tunneling field-effect transistors. IEEE Electron Device Lett. 31(8), 779–781 (2010). https://doi.org/10.1109/LED.2010.2050456
G.F. Jiao, X.Y. Huang, Z.X. Chen, W. Cao, D. Huang, H.Y. Yu, N. Singh, G.Q. Lo, D.L. Kwong, M.-F. Li, Investigation of tunneling field effect transistor reliability, 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, pp. 1612–1615, (2010). https://doi.org/10.1109/ICSICT.2010.5667426
G.B. Beneventi, E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani, Can interface traps suppress TFET ambipolarity? IEEE Electron Device Lett. 34(12), 1557–1559 (2013). https://doi.org/10.1109/LED.2013.2284290
Y. Qiu, R. Wang, Q. Huang, R. Huang, A comparative study on the impacts of interface traps on tunneling FET and MOSFET. IEEE Trans. Electron Devices 61(5), 1284–1291 (2014). https://doi.org/10.1109/TED.2014.2312330
K.E. Moselund, D. Cutaia, H. Schmid, M. Borg, S. Sant, A. Schenk, H. Riel, Lateral InAs/Si p-type tunnel FETs integrated on Si—part 1: experimental devices. IEEE Trans. Electron Devices 63(11), 4233–4239 (2016). https://doi.org/10.1109/TED.2016.2606762
S. Sant, K. Moselund, D. Cutaia, H. Schmid, M. Borg, H. Riel, A. Schenk, Lateral InAs/Si p-type tunnel FETs integrated on Si—part 2: simulation study of the impact of interface traps. IEEE Trans. Electron Devices 63(11), 4240–4247 (2016). https://doi.org/10.1109/TED.2016.2612484
J. Madan, R. Chaujar, Numerical simulation of N+ source pocket PIN-GAA-tunnel FET: impact of interface trap charges and temperature. IEEE Trans. Electron Devices 64(4), 1482–1488 (2017). https://doi.org/10.1109/TED.2017.2670603
P. Venkatesh, K. Nigam, S. Pandey, D. Sharma, P. Kondekar, Impact of interface trap charges on performance of electrically doped tunnel FET with heterogeneous gate dielectric. IEEE Trans. Device Mater. Reliab. 17(1), 245–252 (2017). https://doi.org/10.1109/TDMR.2017.2653620
A.M. Walke, A.S. Verhulst, A. Vandooren, D. Verreck, E. Simoen, V.R. Rao, G. Groeseneken, N. Collaert, A.V.Y. Thean, Part I: impact of field-induced quantum confinement on the subthreshold swing behavior of line TFETs. IEEE Trans. Electron Devices 60(12), 4057–4064 (2013). https://doi.org/10.1109/TED.2013.2287259
A.M. Walke, A. Vandooren, B. Kaczer, A.S. Verhulst, R. Rooyackers, E. Simoen, M.M. Heyns, V.R. Rao, G. Groeseneken, N. Collaert, A.V.Y. Thean, Part II: investigation of subthreshold swing in line tunnel FETs using bias stress measurements. IEEE Trans. Electron Devices 60(12), 4065–4072 (2013). https://doi.org/10.1109/TED.2013.2287253
P. Ghosh, A. Roy, B. Bhowmick, The impact of donor/acceptor types of interface traps on selective buried oxide TFET characteristics. Appl. Phys. A 126(5), 1–7 (2020). https://doi.org/10.1007/s00339-020-03505-6
K. Baruah, R. Das, S. Baishya, Impact of trap charge and temperature on DC and Analog/RF performances of hetero structure overlapped PNPN tunnel FET. Appl. Phys. A 126(11), 1–12 (2020). https://doi.org/10.1007/s00339-020-04054-8
J. Franco, A. Alian, A. Vandooren, A.S. Verhulst, D. Linten, N. Collaert, A. Thean, Intrinsic robustness of TFET subthreshold swing to interface and oxide traps: a comparative PBTI study of InGaAs TFETs and MOSFETs. IEEE Electron Device Lett. 37(8), 1055–1058 (2016). https://doi.org/10.1109/LED.2016.2584983
M. Akasaka, T. Lida, A. Matsumoto, K. Yamanaka, Y. Takanashi, T. Imai, N. Hamada, The thermoelectric properties of bulk crystalline n-and p-type Mg2Si prepared by the vertical Bridgman method. Appl. Phys. 104(1), 013703 (2008). https://doi.org/10.1063/1.2946722
N. Hirayama, T. Iida, M. Sakamoto, K. Nishio, N. Hamada, Substitutional and interstitial impurity p-type doping of thermoelectric Mg2Si: a theoretical study. Sci. Technol. Adv. Mater. 20(1), 160–172 (2019). https://doi.org/10.1080/14686996.2019.1580537
A. Tura, Z. Zhang, P. Liu, Y.H. Xie, J.C. Woo, Vertical silicon pnpn tunnel nMOSFET with MBE-grown tunneling junction. IEEE Trans. Electron Devices 58(7), 1907–1913 (2011). https://doi.org/10.1109/TED.2011.2148118
M. Pala, D. Esseni, F. Conzatti, Impact of interface traps on the IV curves of InAs tunnel-FETs and MOSFETs: a full quantum study, IEEE International Electron Devices Meeting (IEDM), pp. 6–6, (2012). https://doi.org/10.1109/IEDM.2012.6478992
G.F. Jiao, Z.X. Chen, H.Y. Yu, X.Y. Huang, D.M. Huang, N. Singh, G.Q. Lo, D.L. Kwong, M.F. Li, New degradation mechanisms and reliability performance in tunneling field effect transistors, IEEE International Electron Devices Meeting (IEDM), pp. 1–4, (2009). https://doi.org/10.1109/IEDM.2009.5424 234
E.H. Poindexter, MOS interface states: overview and physicochemical perspective. Semicond. Sci. Technol. 4(12), 961 (1989). https://doi.org/10.1088/0268-1242/4/12/001
L. Trabzon, O.O. Awadelkarim, Damage to n-MOSFETs from electrical stress relationship to processing damage and impact on device reliability. Microelectron. Reliab. 38(4), 651–657 (1998). https://doi.org/10.1016/S0026-2714(97)00194-7
Y. Wu, K. Kakushima, Y. Takahashi, Formation of magnesium silicide for source material in Si based tunnel FET by annealing of Mg/Si thin film multi-stacks, 17th International Workshop on Junction Technology (IWJT), IEEE, pp. 83–84, (2017). https://doi.org/10.23919/IWJT.2017.7966522
S. Guha, P. Pachal, S. Ghosh, S.K. Sarkar, Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance. Superlattices Microstruct. 146, 106657 (2020). https://doi.org/10.1016/j.spmi.2020.106657
V. Brouzet, B. Salem, P. Periwal, R. Alcotte, F. Chouchane, F. Bassani, T. Baron, G. Ghibaudo, Fabrication and electrical characterization of homo-and hetero-structure Si/SiGe nanowire tunnel field effect transistor grown by vapor–liquid–solid mechanism. Solid State Electron. 118, 26–29 (2016). https://doi.org/10.1016/j.sse.2016.01.005
K.K. Bhuwalka, S. Sedlmaier, A.K. Ludsteck, C. Tolksdorf, J. Schulze, I. Eisele, Vertical tunnel field-effect transistor. IEEE Trans. Electron Devices 51(2), 279–282 (2004). https://doi.org/10.1109/TED.2003.821575
W.Y. Choi, H.K. Lee, Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). Nano Converg. 3(1), 1–15 (2016). https://doi.org/10.1186/s40580-016-0073-y
J.W. Lee, W.Y. Choi, Design guidelines for gate-normal hetero-gate-dielectric (GHG) tunnel field-effect transistors (TFETs). IEEE Access 8, 67617–67624 (2020). https://doi.org/10.1109/ACCESS.2020.2985125
K.S. Singh, S. Kumar, K. Nigam, Impact of interface trap charges on analog/RF and linearity performances of dual-material gate-oxide-stack double-gate TFET. IEEE Trans. Device Mater. Reliab. (2020). https://doi.org/10.1109/TDMR.2020.2984669
A.K. Singh, M.R. Tripathy, K. Baral, P.K. Singh, S. Jit, Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate. Appl. Phys. A 126(9), 1–11 (2020). https://doi.org/10.1007/s00339-020-03869-9
S. Mookerjea, R. Krishnan, S. Datta, V. Narayanan, On enhanced Miller capacitance effect in interband tunnel transistors. IEEE Electron Device Lett. 30(10), 1102–1104 (2009). https://doi.org/10.1109/LED.2009.2028907
S. Gupta, K. Nigam, S. Pandey, D. Sharma, P.N. Kondekar, Effect of interface trap charges on performance variation of heterogeneous gate dielectric junctionless-TFET. IEEE Trans. Electron Devices 64(11), 4731–4737 (2017). https://doi.org/10.1109/TED.2017.2754297
K. Pradhan, S.K. Mohapatra, P. Sahu, D. Behera, Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET. Microelectron. J. 45(2), 144–151 (2014). https://doi.org/10.1016/j.mejo.2013.11.016
Acknowledgements
Authors would like to thank Vice Chancellors of Chitkara University, Punjab and Chitkara University, Himachal Pradesh for their support and permission to communicate this research paper. All the members of VLSI Center of Excellence, Chitkara University, Punjab are thanked for their time to engage in valuable discussions related to this work. Dr Rahul Pandey acknowledges the support from DST SRG to procure SILVACO ATLAS tool with file no. SRG/2019/000941.
Author information
Authors and Affiliations
Corresponding authors
Ethics declarations
Conflict of interest
The authors declare that they have no conflict of interest.
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Dassi, M., Madan, J., Pandey, R. et al. Impact of interfacial charges on analog and RF performance of Mg2Si source heterojunction double-gate tunnel field effect transistor. J Mater Sci: Mater Electron 32, 23863–23879 (2021). https://doi.org/10.1007/s10854-021-06823-4
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10854-021-06823-4