Skip to main content
Log in

Stressor SiNx contact etch stop layer (CESL) technology and its application in nano-scale transistors

  • Published:
Journal of Materials Science: Materials in Electronics Aims and scope Submit manuscript

Abstract

The high stress SiNx thin film deposition technology is widely used in nano-scale transistor structure to induce strain and improve the carrier transport in the channel region. In this work, the synthesis and process of high tensile stress SiNx thin films have been studied. High tensile stress SiNx thin film is obtained by multiple treatment of N2 plasma. The optimized SiNx films was integrated into the 26 nm transistors and found that the driving current Idsat was improved by 27%.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7

Similar content being viewed by others

References

  1. E. Parton, P. Verheye, Strained silicon—the key to sub-45 nm CMOS. III-Vs Rev. 19, 28–31 (2006)

    Google Scholar 

  2. G.L. Wang. Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond (Springer, Singapore, 2019)

    Book  Google Scholar 

  3. K.J. Kuhn. CMOS scaling for the 22 nm node and beyond: Device physics and technology, in Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications, Hsinchu, (2011), pp. 1–2

  4. G. Wang, M.Moeen,A. Abedin et al., Optimization of SiGe selective epitaxy for source/drain engineering in 22 nm node complementary metal-oxide semiconductor (CMOS). J. Appl. Phys. 114(12), 123511 (2013)

    Article  Google Scholar 

  5. G. Wang, C. Qin, H. Yin et al., Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14 nm nodes FinFET technology. Microelectron. Eng. 163, 49–54 (2016)

    Article  CAS  Google Scholar 

  6. H.H. Radamaon, M. Kolahdouz, Selective epitaxy growth of Si1-x Gex layers for MOSFETs and FinFET. J. Mater. Sci.: Mater. Electron. 26, 4584–4603 (2015)

    Google Scholar 

  7. M. Wiatr, T. Feudel, A. Wei et al. Review on Process-Induced Strain Techniques for Advanced Logic Technologies, in International Conference on Advanced Thermal Processing of Semiconductors, (2007), pp. 19–29

  8. H.H. Radamson, Y. Zhang, X. He et al., The challenges of advanced CMOS process from 2D to 3D. Appl. Sci. 7(10), 1047 (2017)

    Article  Google Scholar 

  9. H.H. Radamson, Monolithic Nanoscale Photonics-Electronics Integration in Silicon and Other Group IV Elements (Academic Press, Cambridge, 2014)

    Google Scholar 

  10. S. Natarajan, M. Armstrong, M. Bost et al. A 32 nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171 µm2 SRAM cell size in a 291 Mb array. Electron Devices Meeting, (2008)

  11. J.Pham C.Yang. Characteristic Study of Silicon Nitride Films Deposited by LPCVD and PECVD. Silicon, 10(6), 2561–2567 (2018)

    Article  Google Scholar 

  12. S.L. Zhang, J.T. Wang, W. Kaplan, M. Östling, Silicon nitride films deposited from SiH2Cl2 ·NH3 by low pressure chemical vapor deposition: kinetics, thermodynamics, composition and structure. Thin Solid Films 213, 182–191 (1992)

    Article  CAS  Google Scholar 

  13. M. Leskela, M.Ritala. Atomic layer deposition (ALD): from precursors to thin film structures. Thin Solid Films 409(1), 138–146 (2002)

    Article  CAS  Google Scholar 

  14. H. Huang, K.J. Winchester, A.Suvorova, et al. Effect of deposition conditions on mechanical properties of low-temperature PECVD silicon nitride films. Mater. Sci. Eng. A 435, 453-459 (2006)

    Article  Google Scholar 

  15. V. Jayan, D. Alok, P.R. Vaya. Growth of silicon nitride by PECVD, in Proceedings of Spie the International Society for Optical Engineering, vol. 1523, (1992), pp. 546–554

  16. L. Liu, W. Liu, N. Cao et al., Study on the performance of PECVD silicon nitride thin films. Def. Technol. 9(2), 121–126 (2013)

    Article  Google Scholar 

  17. R. Arghavani et al., A reliable and manufacturable method to induce a stress of > 1 GPa on a P-channel MOSFET in high volume manufacturing. IEEE Electron. Device Lett. 27(2), 114–116 (2006)

    Article  CAS  Google Scholar 

  18. S. Deleonibus, Physical and technological limitations of NanoCMOS devices to the end of the roadmap and beyond. Eur. Phys. J.-Appl. Phys. 36(3), 197–214 (2006)

    Article  CAS  Google Scholar 

  19. H.H. Radamson, X. He, Q. Zhang et al., Miniaturization of CMOS. Micromachines 10(5), 293 (2019)

    Article  Google Scholar 

  20. B.C. Joshi, G. Eranna et al., LPCVD and PECVD silicon nitride for microelectronics technology. Indian J. Eng. Mater. Sci. 7(5), 303–309 (2000)

    CAS  Google Scholar 

  21. H.H. Radamson, E. Simoen, J. Luo, C. Zhao, Past, Present and Future of CMOS (Elsevier, Amsterdam, 2018)

    Google Scholar 

  22. K.J. Kuhn, Moore’s Law Past 32nm: Future Challenges in Device Scaling. International Workshop on Computational Electronics ( IEEE, Piscataway, 2009), pp. 1–6

    Google Scholar 

  23. H.S. Yang, R. Malik, S.Narasimha, et al. Dual stress liner for high performance sub-45 nm gate length SOI CMOS manufacturing. International electron devices meeting, (2004), pp. 1075–1077

  24. P. Nguyen, S.Barraud, C.Tabone, et al. Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15 nm gate length. Electron Devices Meeting. IEEE (2014)

  25. A. Gupta, C. Gupta, A.K.Bansal, et al. Stressor efficacy and mobility enhancement in N-channel nanowire FETs, in International Conference on Electron Devices and Solid-state Circuits, (2017), pp. 1–2

Download references

Acknowledgements

This work was supported in part by the National Key Project of Science and Technology of China (Grant No. 2017ZX02315001-002), in part by the projects of the construction of new research and development institutions (Grant No. 2019B090904015) and the construction of high-level innovation research institute from the Guangdong Greater Bay Area Institute of Integrated Circuit and System (Grant No. 2019B090909006), in part by the National Key Research and Development Program of China (Grant No. 2016YFA0301701), and the Youth Innovation Promotion Association of CAS under Grant No. 2016112.

Author information

Authors and Affiliations

Authors

Corresponding authors

Correspondence to Wenjuan Xiong or Guilei Wang.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Xu, Q., Xiong, W., Wang, G. et al. Stressor SiNx contact etch stop layer (CESL) technology and its application in nano-scale transistors. J Mater Sci: Mater Electron 31, 10078–10083 (2020). https://doi.org/10.1007/s10854-020-03553-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10854-020-03553-x

Navigation