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Study of selective isotropic etching Si1−xGex in process of nanowire transistors

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Abstract

On approach towards the end of technology roadmap, a revolutionary approach towards the nanowire transistors is favorable due to the full control of carrier transport. The transistor design moves toward vertically or laterally stacked Gate-All-Around (GAA) where Si or SiGe can be used as channel material. This study presents a novel isotropic inductively coupled plasma (ICP) dry etching of Si1−xGex (0.10 ≤ x ≤ 0.28) in SiGe/Si multilayer structures (MLSs) with high selectivity to Si, SiO2, Si3N4 and SiON which can be applied in advanced 3D transistors and Micro-Electro-Mechanical System (MEMS) in future. The profile of SiGe etching for different thicknesses, compositions and locations in MLSs using dry or wet etch have been studied. A special care has been spent for layer quality of Si, strain relaxation of SiGe layers as well as residual contamination during the etching. In difference with dry etching methods (downstream remote plasma), the conventional ICP source in situ is used where CF4/O2/He gas mixture was used as the etching gas to obtain higher selectivity. Based on the reliability of ICP technique a range of etching rate 25–50 nm/min can be obtained for accurate isotropic etching of Si1−xGex, to form cavity in advanced 3D transistor processes in future.

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Abbreviations

GAA:

Gate All Around

ICP:

Inductively coupled plasma

MEMS:

Micro Electro Mechanical System

V-GAA:

Vertical Gate-All-Around

L-GAA:

Lateral Gate-All-Around

NWS:

Nanowire structure

MLS:

Multilayer structure

FinFET:

Fin Field-Effect Transistor

RPCVD:

Reduced pressure chemical vapor deposition

HRSEM:

High-resolution scanning electron microscope

HRTEM:

High-resolution transmission electron microscope

HRXRD:

High resolution x-ray diffraction

EDS:

Energy dispersive spectrometer

HRRLM:

High-resolution reciprocal lattice mapping

References

  1. Colinge, J.P., Gao, M.H., Romano-Rodriguez, A., et al.: Silicon-on-insulator “gate-all-around device”. In: International Technical Digest on Electron Devices IEEE, pp. 595–598 (1990)

  2. I. Ferain, C.A. Colinge, J.-P. Colinge, Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature 479, 310–316 (2011)

    Article  CAS  Google Scholar 

  3. H.H. Radamson, Y. Zhang, X. He et al., The challenges of advanced CMOS process from 2D to 3D. Appl. Sci. 1047, 1–32 (2017)

    Google Scholar 

  4. V. Pott, K.E. Moselund, D. Bouvet, L. De Michielis, A.M. Ionescu et al., Fabrication and characterization of gate-all-around silicon nanowires on bulk silicon. IEEE Trans. Nanotechnol. 7(6), 733–743 (2008)

    Article  Google Scholar 

  5. D.-I. Moon, S.-J. Choi, J.P. Duarte et al., Investigation of silicon nanowire gate-all-around junctionless transistors built on a bulk substrate. IEEE Trans. Electron Devices 60(4), 1355–1360 (2013)

    Article  CAS  Google Scholar 

  6. Zhang, Q., Yin, H., Luo, J., et al.: FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin. In: Electron Devices Meeting, 2016. IEEE International, pp. 17.3.1–17.3.4 (2016)

  7. Q. Zhang, H. Yin, L. Meng et al., Novel GAA Si nanowire p-MOSFETs with excellent short channel effect immunity via an advanced forming process. IEEE Electron Device Lett. 39(4), 464–467 (2018)

    Article  CAS  Google Scholar 

  8. Yeo, K.H., Suk, S.D., Li, M., et al.: Gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires. In: Electron Devices Meeting, 2006. IEEE International, pp. 1–4 (2006)

  9. Bera, L.K., Nguyen, H.S., Singh, N., et al.: Three dimensionally stacked SiGe nanowire array and gate-all-around p-MOSFETs. In: Electron Devices Meeting, 2006. IEEE International, pp. 1–4 (2006)

  10. Mertens, H., Ritzenthaler, R., Chasin, A., et al.: Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates. In: Electron Devices Meeting, 2016. IEEE International, pp. 19.7.1–19.7.4 (2016)

  11. Barraud, S., Lapras, V., Samson, M.P., et al.: Vertically stacked-nanowires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain. In: Electron Devices Meeting, 2016. IEEE International, pp. 17.6.1–17.6.3 (2016)

  12. Mertens, H., Ritzenthaler, R., Pena, V., et al.: Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration. In: Electron Devices Meeting. IEEE International, pp. 37.4.1–37.4.4(2017)

  13. Loubet, N., Hook, T., Montanini, P., et al.: Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. In: Symposium on VLSI Technology, pp. T230–T231 (2017)

  14. F.S. Johnson, D.S. Miles, D.T. Grider et al., Selective chemical etching of polycrystailine SiGe alloys with respect to Si and SiO2. J. Electron. Mater. 21(8), 805–810 (1992)

    Article  CAS  Google Scholar 

  15. B. Holländer, D. Buca, S. Mantl et al., Wet chemical etching of Si, Si1−xGex, and Ge in HF:H2O2:CH3COOH. J. Electrochem. Soc. 157(6), H643–H646 (2010)

    Article  Google Scholar 

  16. Y.-H. Kil, J.-H. Yang, S. Kang et al., Selective chemical wet etching of Si0.8Ge0.2/Si multilayer. J. Semicond. Technol. Sci. 13(6), 668–674 (2013)

    Article  Google Scholar 

  17. M. Kolahdouz, L. Maresca, R. Ghandi et al., Kinetic model of SiGe selective epitaxial growth using RPCVD technique. J. Electrochem. Soc. 158(4), H457–H464 (2011)

    Article  CAS  Google Scholar 

  18. N. Loubet, T. Kormann, G. Chabanne et al., Selective etching of Si1−xGex versus Si with gaseous HCl for the formation of advanced CMOS devices. Thin Solid Films 517, 93–97 (2008)

    Article  CAS  Google Scholar 

  19. Y. Bogumilowicz, J.M. Hartmann, R. Truche et al., Chemical vapour etching of Si, SiGe and Ge with HCl; applications to the formation of thin relaxed SiGe buffers and to the revelation of threading dislocations. Semicond. Sci. Technol. 20(2), 127 (2004)

    Article  Google Scholar 

  20. J.M. Hartmann, V. Destefanis, G. Rabill et al., HCl selective etching of SiGe versus Si in stacks grown on (1 1 0). Semicond. Sci. Technol. 25(10), 105009 (2010)

    Article  Google Scholar 

  21. S. Borel, C. Arvet, J. Bilde et al., Control of Selectivity between SiGe and Si in isotropic etching processes. Jpn. J. Appl. Phys. 43(6), 3964–3966 (2004)

    Article  CAS  Google Scholar 

  22. C. Beylier, S. Borel, O. Renault et al., Mechanisms of isotropic and selective etching between SiGe and Si. J. Vac. Sci. Technol. 24(6), 2748–2754 (2006)

    Article  Google Scholar 

  23. M.D. Henry, E.A. Douglas et al., Chemical downstream etching of Ge, Si, and SiNx films. J. Vac. Sci. Technol. 34(5), 0520031-1 (2016)

    Google Scholar 

  24. M.S.B. Castro, S. Barnola, B. Glück et al., Selective and anisotropic dry etching of Ge over Si. J. Integr. Circuits Syst 8(2), 104–109 (2013)

    Google Scholar 

  25. S. Borel, C. Arvet, J. Bilde et al., Isotropic etching of SiGe alloys with high selectivity to similar materials. Microelectron. Eng. 73(74), 301–305 (2004)

    Article  Google Scholar 

  26. C.F. Ahles, J.Y. Choi, S. Wolf et al., Selective etching of silicon in preference to germanium and Si0.5Ge0.5. ACS Appl. Mater. Interfaces. 9, 20947–20954 (2017)

    Article  CAS  Google Scholar 

  27. Q. Zhang, H. Tu, S. Gu et al., Influence of rapid thermal annealing on Ge-Si interdiffusion in epitaxial multilayer Ge0.3Si0.7/Si superlattices with various GeSi thicknesses. ECS J. Solid State Sci. Technol. 7(11), P671–P676 (2018)

    Article  CAS  Google Scholar 

  28. G. Wang, A. Ahmad, M. Mahdi et al., Integration of highly-strained SiGe materials in 14 nm and beyond nodes FinFET technology. Solid-State Electron. 103, 222–228 (2015)

    Article  CAS  Google Scholar 

  29. G. Wang, J. Luo, C. Qin et al., Integration of highly strained SiGe in source and drain with HK and MG for 22 nm bulk PMOS transistors. Nanoscale Res. Lett. 12(1), 123 (2017)

    Article  Google Scholar 

  30. Radamson, H.H., Luo, J., Simeon, E., Chao Z.: Past, Present and Future of CMOS. Elsevier (2018)

  31. Radamson, H.H., Thylen L.: Monolithic Nanoscale Photonics-Electronics Integration in Silicon and Other Group 1 V Elements. Elsevier (2014)

  32. Z. Liu, X. Dehui, C. Zhou et al., Effects of the pulse polarity on helium plasma jets: discharge characteristics, key reactive species, and inactivation of myeloma cell. Plasma Chem. Plasma Process. 38, 953 (2018)

    Article  CAS  Google Scholar 

  33. J. Ding, J.-S. Jenq, G.-H. Kim et al., Etching rate characterization of SiO2 and Si using ion energy flux and atomic fluorine density in a CF4/O2/Ar electron cyclotron resonance plasma. J. Vac. Sci. Technol. 11(4), 1283–1288 (1993)

    Article  CAS  Google Scholar 

  34. D. Lee, P. Tatti, R. Lee et al., Study for new hardmask process scheme, in Advances in Patterning Materials and Processes XXXIV. International Society for Optics and Photonics, vol 10146 (2017), p. 101461L

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Acknowledgements

This work was financially supported by the science and technology planning project of Beijing (Z191100010618005), the National Key Project of Science and Technology of China (Grant No. 2017ZX02315001-002) and the National Key Research and Development Program of China (Grant No. 2016YFA0301701).

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Authors and Affiliations

  1. University of Chinese Academy of Sciences, Beijing, 100049, People’s Republic of China

    Junjie Li, Wenwu Wang, Guilei Wang, Zhenzhen Kong, Jianyu Fu, Xiaogen Yin, Chen Li, Huaxiang Yin, Huilong Zhu & Henry H. Radamson

  2. Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, People’s Republic of China

    Junjie Li, Wenwu Wang, Yongliang Li, Na Zhou, Guilei Wang, Jianyu Fu, Xiaogen Yin, Chen Li, Xiaolei Wang, Hong Yang, Xueli Ma, Jianghao Han, Tao Yang, Junfeng Li, Huaxiang Yin, Huilong Zhu & Henry H. Radamson

  3. College of Electronic and Information Engineering, North China University of Technology, Beijing, 100144, China

    Jing Zhang, Yijun Wei & Tairan Hu

  4. Department of Electronics Design, Mid Sweden University, Holmgatan 10, 85170, Sundsvall, Sweden

    Henry H. Radamson

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  1. Junjie Li
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Correspondence to Wenwu Wang or Guilei Wang.

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Li, J., Wang, W., Li, Y. et al. Study of selective isotropic etching Si1−xGex in process of nanowire transistors. J Mater Sci: Mater Electron 31, 134–143 (2020). https://doi.org/10.1007/s10854-019-02269-x

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