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Maximal Connectivity Test with Channel-Open Faults in On-Chip Communication Networks

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Abstract

The networks-on-chip (NoCs) as the prevalent interconnection infrastructure have been continuously replacing the contemporary chip microprocessors (CMPs) while high performance computing is the dominant consideration. Aggressive technology scaling progressively reduces the feature size of the chips resulting in increasing susceptibility to failures and breakdowns due to open faults on communication channels. The reliability and performance issues are then becoming more critical requirement in both current and future NoC-based CMPs. This paper first presents an on-line, distributed built-in-self-test (BIST) oriented test mechanism that particularly detects open faults on communication channels and identifies faulty wires from the channels in NoCs. Next, a suitable test scheduling scheme is presented in order to reduce the overall test time and related performance overhead due the fault. Such scheduling scheme makes the present test solution scalable with large scale NoC architectures in general. Implementation of the test mechanism takes little hardware area and few clocks to detect the fault in channels. The on-line evaluation of the proposed test solution demonstrates the effect of the channel-open faults on the NoC performance characteristics at large real like synthetic traffic. In comparison to wide range of prior works on 16-bit networks, the present scheme provides many advantages, e.g., it improves hardware area overhead by 35.36–67.73% and saves the test time by 96.43%. packet latency and energy consumption by 5.83–42.79% and 6.24–46.38%, respectively on the networks, the proposed scheme becomes competitive with the existing works.

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Notes

  1. A hop is single channel length.

References

  1. Hoskote Y, Vangal S, Singh A, Borkar N, Borkar S (2007) A 5-ghz mesh interconnect for a teraflops processor. IEEE Micro 27(5):51–61

    Article  Google Scholar 

  2. Wentzlaff D, Griffin P, Hoffmann H, Bao L, Edwards B, Ramey C, Mattina M, Miao C. -C., Brown IIIJF, Agarwal A (2007) On-chip interconnection architecture of the tile processor. IEEE Micro 27:15–31

    Article  Google Scholar 

  3. Runge A (2015) Fault-tolerant network-on-chip based on fault-aware flits and deflection routing. In: Proceedings of the 9th international symposium on networks-on-chip (NOCS). ACM, NY, pp 9:1–9:8

  4. Chittamuru SVR, Desai S, Pasricha S (2017) Swiftnoc: a reconfigurable silicon-photonic network with multicast-enabled channel sharing for multicore architectures. J Emerg Technol Comput Syst 13:58:1–58:27

    Article  Google Scholar 

  5. Bhowmik B, Deka JK, Biswas S (2015) Reliability on top of best effort delivery: Maximal connectivity test on noc interconnects. In: Proceedings of the 8th annual ACM India conference, compute ’15, (new york, NY, USA), pp 19–28, ACM

  6. Bhowmik B, Deka JK, Biswas S, Bhattacharya BB (2019) Performance-aware test scheduling for diagnosing coexistent channel faults in topology-agnostic networks-on-chip. ACM Trans Des Autom Electron Syst 24:17:1–17:29

    Article  Google Scholar 

  7. Liu J, Harkin J, Li Y, Maguire L (2014) Online traffic-aware fault detection for networks-on-chip. J Parallel Distrib Comput 74(1):1984–1993

    Article  Google Scholar 

  8. Hu C, Li Z, Xu C, Jia M (2016) Test scheduling for network-on-chip using xy-direction connected subgraph partition and multiple test clocks. J Electron Test 32:31–42

    Article  Google Scholar 

  9. Dalirsani A, Wunderlich HJ (2016) Functional diagnosis for graceful degradation of noc switches. In: Proceedings of the IEEE 25th asian test symposium (ATS), pp 246–251

  10. Xiang D, Chakrabarty K, Fujiwara H (2016) A unified test and fault-tolerant multicast solution for network-on-chip designs In: IEEE International test conference (ITC).IEEE, pp 1–9

  11. Xiang D, Shen K (2016) A new unicast-based multicast scheme for network-on-chip router and interconnect testing. ACM Trans Des Autom Electron Syst 21(2):24/1–24/23

    Article  MathSciNet  Google Scholar 

  12. Xiang D, Chakrabarty K, Fujiwara H (2018) Fault-tolerant unicast-based multicast for reliable network-on-chip testing. ACM Trans Des Autom Electron Syst 23(6):73/1–73/23

    Article  Google Scholar 

  13. Herve M, Moraes M, Almeida P, Lubaszewski M, Kastensmidt F, Cota E (2011) Functional test of mesh-based nocs with deterministic routing: Integrating the test of interconnects and routers. J Electron Test 27 (5):635–646

    Article  Google Scholar 

  14. Concatto C, Almeida J, Fachini G, Herve M, Kastensmidt F, Cota E, Lubaszewski M (2011) Improving the yield of noc-based systems through fault diagnosis and adaptive routing. J Parallel Distrib Comput 71:664–674

    Article  Google Scholar 

  15. Caselli N, Strano A, Ludovici D, Bertozzi D (2012) Cooperative built-in self-testing and self-diagnosis of noc bisynchronous channels. In: Proceedings of the IEEE 6th international symposium on embedded multicore socs (MCSoc), pp 159–166

  16. Kakoee M, Bertacco V, Benini L (2014) At-speed distributed functional testing to detect logic and delay faults in nocs. IEEE Trans Comput 63:703–717

    Article  MathSciNet  Google Scholar 

  17. Bhowmik B, Biswas S, Deka JK (2015) A packet address driven test strategy for stuck-at faults in networks-on-chip interconnects. In: Proceedings of the IEEE 23rd mediterranean conference on control and automation (MED), pp 176–183

  18. Bhowmik B, Deka JK, Biswas S (2015) An odd-even model for diagnosis of shorts on noc interconnects. In: Proceedings of the IEEE 12th India conference (INDICON), pp 1–6

  19. Bhowmik B, Biswas S, Deka JK (2016) Impact of noc interconnect shorts on performance metrics. In: Proceedings of the IEEE 22nd national conference on communication (NCC), pp 1–6

  20. Bhowmik B, Deka JK, Biswas S, Bhattacharya BB (2019) A low-cost test solution for reliable communication in networks-on-chip, Journal of Electronic Testing, vol 35, pp 215–243

  21. Bhowmik B, Biswas S, Deka JK (2016) On-line testing of coexistent stuck-at and open faults in noc interconnects. In: Proceedings of the IEEE 36th region 10 conference (TENCON), pp 157–162

  22. Bhowmik B, Biswas S, Deka JK, Bhattacharya BB (Oct 2016) Detecting and diagnosing open faults in noc channels on activation of diagonal nodes. In: Proceedings of the IEEE 29th international conference on systems, man, and cybernetics (SMC), pp 4573–4578

  23. Ghiribaldi A, Ludovici D, Triviño F, Strano A, Flich J, Sánchez J. L., Alfaro F, Favalli M, Bertozzi D (2013) A complete self-testing and self-configuring noc infrastructure for cost-effective mpsocs. ACM Trans Embedded Comput Syst (TECS) 12(4):106

    Google Scholar 

  24. Bhowmik B, Deka JK, Biswas S (2016) A concurrent approach to detect and diagnose shorts in interconnects of on-chip networks. In: Proceedings of the IEEE 36th region 10 conference (TENCON), pp 2418–2423

  25. Chen YH, Chang CL, Wen CHP (2012) Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow. IET Comput Digit Techn 6:186–193

    Article  Google Scholar 

  26. Xue H, Di C, Jess JAG (1994) Probability analysis for cmos floating gate faults. In: Proceedings of the european design and test conference EDAC-ETC-EUROASIC, pp 443–448

  27. Spinner S, Polian I, Engelke P, Becker B, Keim M, Cheng W-T (2008) Automatic test pattern generation for interconnect open defects. In: Proceedings of the 26th IEEE VLSI test symposium (VTS), pp 181–186

  28. Bhowmik B, Biswas S, Deka JK, Bhattacharya BB (2018) Reliability-aware test methodology for detecting short-channel faults in on-chip networks. IEEE Trans Very Large Scale Integr (VLSI) Syst 26:1–14

    Article  Google Scholar 

  29. Flich J, Bertozzi D (2010) Designing Network On-Chip Architectures in the Nanoscale Era Chapman & Hall/CRC

  30. Karim F, Nguyen A, Dey S (2002) An interconnect architecture for networking systems on chips. IEEE Micro 22:36–45

    Article  Google Scholar 

  31. Bhowmik B (2019) A power-aware fault detection scheme for 2d mesh-based network-on-chip interconnects. J Low Power Electron 15(2):256–272

    Article  Google Scholar 

  32. Zeferino C, Kreutz M (2004) A Susin, RASoc: a router soft-core for networks-on-chip. In: Proceedings of the design, automation and test in europe conference and exhibition, vol 3, pp 198–203

  33. Moraes F, Calazans N, Mello A, Möller L., Ost L (2004) Hermes: an infrastructure for low area overhead packet-switching networks on chip. Integr VLSI J 38(1):69–93

    Article  Google Scholar 

  34. Bertozzi D, Benini L (2004) Xpipes: a network-on-chip architecture for gigascale systems-on-chip. IEEE Circ Syst Mag 4(2): 18–31

    Article  Google Scholar 

  35. Goossens K, Dielissen J, Radulescu A (2005) Aethereal network on chip: concepts, architectures, and implementations. IEEE Des. Test 22:414–421

    Article  Google Scholar 

  36. Fick D, DeOrio A, Hu J, Bertacco V, Blaauw D, Sylvester D (2009) Vicis: a reliable network for unreliable silicon. In: Proceedings of the 46th annual design automation conference, DAC ’09. ACM, NY, pp 812–817

  37. Catania V, Mineo A, Monteleone S, Palesi M, Patti D (2016) Cycle-accurate network on chip simulation with Noxim. ACM Trans Model Comput Simul 27:4:1–4:25

    Article  Google Scholar 

  38. Boppana R. V., Chalasani S (1995) Fault-tolerant wormhole routing algorithms for mesh networks. IEEE Trans Comput 44:848–864

    Article  Google Scholar 

  39. Davidson S, Xie S, Torng C, Al-Hawai K, Rovinski A, Ajayi T, Vega L, Zhao C, Zhao R, Dai S, Amarnath A, Veluri B, Gao P, Rao A, Liu G, Gupta RK, Zhang Z, Dreslinski R, Batten C, Taylor MB (2018) The celerity open-source 511-core risc-v tiered accelerator fabric: Fast architectures and design methodologies for fast chips. IEEE Micro 38:30–41

    Article  Google Scholar 

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  1. Department of Computer Science and Engineering, National Institute of Technology Karnataka, Surathkal, 575025, India

    Biswajit Bhowmik

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Correspondence to Biswajit Bhowmik.

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Bhowmik, B. Maximal Connectivity Test with Channel-Open Faults in On-Chip Communication Networks. J Electron Test 36, 385–408 (2020). https://doi.org/10.1007/s10836-020-05878-1

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