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An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects

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Abstract

Circuit reliability due to Bias Temperature Instability, BTI, has become an important concern in scaled-down complex electronic systems. Even more, current silicon technologies are severely affected by the combined impact of BTI-induced device’s aging and Process-induced device’s parameters variations. The conventional worst-case guardbanding to deal with reliable circuit operation is not longer an efficient approach as the circuit performance is significantly penalized. This paper presents a gate-sizing optimization me-thodology to reduce the worst-case guardbanding considering the combined effects of aging due to BTI and process variations. The proposed methodology allows to trade-off the reduction of guardbanding and the area cost. The proposed methodology uses multiple workload-aware aging analysis procedures to identify a realistic workload condition that causes maximum degradation to each potential critical paths of the circuit. In such a way, classic worst-BTI assumptions that lead to over-design are avoided. New gate-sizing metrics are proposed to identify the most beneficial gates to resize in the delay optimization process. In order to compute the gate sizing metrics efficiently, it is proposed a fast approximation for the sensitivity of the statistical delay of a path with respect to a change in the size of a gate. Also, the criticality, slack-time and area penalization are considered in the metric. A heuristic is proposed to guide the iterative delay optimization process. Some key conditions are identified in the workload analysis, metric evaluation and the heuristic to reduce the computational cost. The results show clearly the benefits of using multiple workload-aware aging analysis and the proposed gate-sizing metrics. It is shown that the proposed gate-sizing metrics are more efficient than others available in the literature since they provide a better area-guardband reduction trade-off. The proposed methodology results in more reliable designs at low area overhead, and it is suitable to guarantee the stringent quality requirements of modern circuits.

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Acknowledgments

This work was supported by CONACYT (Mexico) through the Ph.D. scholarship number 420129/264560.

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Authors and Affiliations

  1. National Institute for Astrophysics, Optics and Electronics (INAOE), Luis Enrique Erro #1, Tonantzintla, Puebla, Mexico

    Andres Gomez & Victor Champac

  2. Universidad Manuela Beltrán (UMB), Calle 33#27–12 Bucaramanga, Santander, Colombia

    Andres Gomez

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  1. Andres Gomez
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  2. Victor Champac
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Correspondence to Andres Gomez.

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Gomez, A., Champac, V. An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects. J Electron Test 35, 87–100 (2019). https://doi.org/10.1007/s10836-019-05772-5

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