Abstract
Due to aggressive technology scaling in electronic of digital integrated circuits, the circuit reliability is becoming an ever-increasing challenge. In nanoscale technologies, the physical and chemical properties of materials are fundamentally different compared to the larger scales. Therefore, it is necessary to revise the conventional reliability assessment techniques considering their applicability to nanoscale integrated circuits. This paper presents a method for evaluating the circuit reliability at the transistor level of abstraction considering the physical characteristics of the transistors. The proposed method considers various parameters, including the probability of different types of a transistor failure, the topology of logic gates and the logical values of the applied input vectors. Experimental results show that the proposed approach provides accurate transistor-level circuit reliability evaluations (with < 4% inaccuracy) as compared to a reference method based on Monte Carlo HSPICE simulations in addition to more than 800 times speedup. Moreover, to show the comprehensiveness and extensibility of the proposed reliability analysis method for the technologies beyond conventional MOSFETs, it is applied to carbon nanotube field-effect transistor (CNFET) technology as one of the most promising candidates for future CMOS circuits. The obtained results re-acknowledge that in order to achieve a more accurate reliability estimation approach for CNFET circuits, it is necessary to consider the open and short failure probability values individually instead of considering them in the form of a single transistor failure probability.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
The International Technology Roadmap for Semiconductors (ITRS) (2009)
Krishnaswamy, S., Viamontes, G., Markov, I., Hayes, J.: Accurate reliability evaluation and enhancement via probabilistic transfer matrices. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 282–28 (2005)
Rejimon, T., Bhanja, S.: Scalable probabilistic computing models using Bayesian networks. In: Proceedings of International Midwest Symposium on Circuits and Systems, pp. 712–715 (2005)
Bahar, I., Mundy, J. L., Chen, J.: A probabilistic-based design methodology for nano-scale computation. In: Proceedings of the 2003 IEEE/ACM International Conference on Computer-Aided Design, pp. 480–486 (2003)
Choudhury, M.R., Mohanram, K.: Reliability analysis of logic circuits. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 28(3), 392–405 (2009)
Han, J., Chen, H., Boykin, E., Fortes, J.: Reliability evaluation of logic circuits using probabilistic gate models. Microelectron. Reliab. 51(2), 468–476 (2011)
Mohyuddi, N., Pakbaznia, E., Pedram, M.: Probabilistic error propagation in logic circuits using the boolean difference calculus. In: Proceedings of International Conference on Computer Design, pp. 7–13 (2008)
Nicolic, K., Sadek, A., Forshaw, M.: Architectures for reliable computing with unreliable nano devices. In: IEEE Conference on Nanotechnology, pp. 254–259 (2001)
El-Maleh, A.H., Al-Hashimi, B.M., Melouki, A., Khan, F.: Defect-tolerant N\(^{2}\)-transistor structure for reliable nano electronic designs. IET Comput. Digit. Tech. 3(6), 570–580 (2009)
McElvain, K.: LGSynth93 Benchmark Set Version 4.0, May (1993)
Chen, H., Han, J.: Stochastic computational models for accurate reliability evaluation of logic circuits. In: Proceedings of the 20th IEEE/ACM Great Lakes Symposium on VLSI, pp. 61–66 (2010)
Raychowdhury, A., Roy, K.: Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol. 4(2), 168–179 (2005)
El-Naggar, A., Mansour, A., Wanass, A., Hassan, S.: Comparative review of carbon nanotube FETs. In: Third International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA), Beirut (2016)
Raychowdhury, A., Roy, K.: Carbon nanotube electronics: design of high-performance and low power digital circuits. IEEE Trans. Circuits Syst. I: Regul. Pap. 54(11), 2391–2401 (2007)
Appenzeller, J., Lin, Y., Knoch, J., Chen, Z., Avouris, P.: Comparing carbon nanotube transistors—the ideal choice: a novel tunneling device design. IEEE Trans. Electron Dev. 52(12), 25, 68-2576 (2005)
Ghavami, B., Raji, M.: Failure characterization of carbon nanotube FETs under process variations: technology scaling issues. IEEE Trans. Dev. Mater. Reliab. 16(2), 164–171 (2016)
Ashraf, R., Chrzanowska-Jeske, M.: Yield estimation of CNFET-based circuits with imperfections. In: 2015 IEEE Nanotechnology Materials and Devices Conference. NMDC, Anchorage, AK (2015)
Zhang, J., Patil, N., Hazeghi, A., Mitra, S.: Carbon nanotube circuits in the presence of carbon nanotube density variations. In: IEEE/ACM Design Automation Conference (DAC), pp. 71–76 (2009)
Sato, H., et al.: Growth of carbon nanotubes on silicon nano-protrusions. Int. Vac. Nanoelectron. Conf. 2005, 268–269 (2005)
Ghavami, B., Raji, M., Pedram, H., Pedram, M.: Statistical functional yield analysis and enhancement of CNFET-based VLSI circuits. IEEE Trans. VLSI Syst. 21(5), 887–900 (2012)
Deng, J., Patil, N., Ryu, K., Badmaev, A., Zhou, C.H., Mitra, S.: Carbon nanotube transistor circuits: circuit-level performance benchmarking and design options for living with imperfections. In: Proceedings on ISSCC, pp. 70–588 (2007)
Ibrahim, W., Beiu, V., Beg, A.: GREDA: a fast and more accurate gate reliability EDA tool. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 31(4), 509–521 (2012)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Saeedi, F., Ghavami, B. & Raji, M. A fast method for process reliability analysis of CNFET-based digital integrated circuits. J Comput Electron 17, 571–579 (2018). https://doi.org/10.1007/s10825-018-1134-8
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10825-018-1134-8