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Heterogate junctionless tunnel field-effect transistor: future of low-power devices

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Abstract

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.

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Authors and Affiliations

  1. Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, 208016, India

    Shiromani Balmukund Rahi & Pranav Asthana

  2. Electronics and Nano-scale Engineering Division, University of Glasgow, Glasgow, UK

    Shoubhik Gupta

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  1. Shiromani Balmukund Rahi
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  2. Pranav Asthana
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  3. Shoubhik Gupta
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Correspondence to Shiromani Balmukund Rahi.

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Rahi, S.B., Asthana, P. & Gupta, S. Heterogate junctionless tunnel field-effect transistor: future of low-power devices. J Comput Electron 16, 30–38 (2017). https://doi.org/10.1007/s10825-016-0936-9

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  • DOI: https://doi.org/10.1007/s10825-016-0936-9

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