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A Coplanar XOR Using NAND-NOR-Inverter and Five-Input Majority Voter in Quantum-Dot Cellular Automata Technology

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Abstract

Quantum-dot cellular automata (QCA) offer a promising design paradigm for complementing conventional integrated circuits. The XOR plays a crucial role in arithmetic circuits and communications. Existing design schemes consume more operational components and thus are inefficient in terms of area and QCA cost at present. In this paper, a coplanar XOR composed of an NAND-NOR-Inverter (NNI) and a five-input majority voter (M5) is proposed for the first time. This new structure not only excludes complex crossovers but also has full accessibility to its input/output pins. The simulation waveforms and performance figures verify the functionality and merits of the proposed circuits. The implementation of the proposed XOR scheme in QCA consumes less overhead than that of its counterparts. Its occupied area and QCA cost are respectively reduced by 9.26% and 33.33% compared with the state-of-the-art XOR. To prove its practicability, multi-bit parity generators are also proposed in the means of hierarchically cascading the proposed XOR gates. The area and cost of the proposed 32-bit generator are respectively reduced by 39.47% and 33.33% compared with the existing best design.

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References

  1. Khouri, K.S., Jha, N.K.: Leakage power analysis and reduction during behavioral synthesis. IEEE Trans. Very Large Scale Integr. VLSI Syst. 10(6), 876–885 (2002). https://doi.org/10.1109/TVLSI.2002.808436

    Article  Google Scholar 

  2. Adan, A.O., Higashi, K., Fukushima, Y.: Analytical threshold voltage model for ultrathin SOI MOSFETs including short-channel and floating-body effects. IEEE Trans. Electron Devices. 46(4), 729–737 (1999). https://doi.org/10.1109/16.753707

    Article  ADS  Google Scholar 

  3. Awano, Y., Sato, S., Nihei, M., Sakai, T., Ohno, Y., Mizutani, T.: Carbon nanotubes for VLSI: interconnect and transistor applications. Proc. IEEE. 98(12), 2015–2031 (2010). https://doi.org/10.1109/JPROC.2010.2068030

    Article  Google Scholar 

  4. Anu, Sharma, A., Khan, M.S., Srivastava, A., Husain, M., Khan, M.S.: High-performance single-electron transistor based on metal–organic complex of thiophene: first principle study. IEEE Trans. Electron Devices. 64(11), 4628–4635 (2017). https://doi.org/10.1109/TED.2017.2756106

    Article  ADS  Google Scholar 

  5. Lent, C.S., Tougaw, P.D.: A device architecture for computing with quantum dots. Proc. IEEE. 85(4), 541–557 (1997). https://doi.org/10.1109/5.573740

    Article  Google Scholar 

  6. Tougaw, P.D., Lent, C.S.: Logical devices implemented using quantum cellular automata. J. Appl. Phys. 75(3), 1818–1825 (1994). https://doi.org/10.1063/1.356375

    Article  ADS  Google Scholar 

  7. Riente, F., Turvani, G., Vacca, M., Roch, M.R., Zamboni, M., Graziano, M.: ToPoliNano: a CAD tool for Nano magnetic logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7), 1061–1074 (2017). https://doi.org/10.1109/TCAD.2017.2650983

    Article  Google Scholar 

  8. Pulimeno, A., Graziano, M., Sanginario, A., Cauda, V., Demarchi, D., Piccinini, G.: Bis-Ferrocene molecular QCA wire: Ab initio simulations of fabrication driven fault tolerance. IEEE Trans. Nanotechnol. 12(4), 498–507 (2013). https://doi.org/10.1109/Tnano.2013.2261824

    Article  ADS  Google Scholar 

  9. Livadaru, L., Xue, P., Shaterzadeh-Yazdi, Z., DiLabio, G.A., Mutus, J., Pitters, J.L., Sanders, B.C., Wolkow, R.A.: Dangling-bond charge qubit on a silicon surface. New J. Phys. 12, 1–15 (2010). https://doi.org/10.1088/1367-2630/aa8b88

    Article  Google Scholar 

  10. Pitters, J.L., Livadaru, L., Haider, M.B., Wolkow, R.A.: Tunnel coupled dangling bond structures on hydrogen terminated silicon surfaces. J. Chem. Phys. 134(6), 1–6 (2011). https://doi.org/10.1063/1.3514896

    Article  Google Scholar 

  11. Kawai, H., Ample, F., Wang, Q., Yeo, Y.K., Saeys, M., Joachim, C.: Dangling-bond logic gates on a Si(100)-(2 x 1)-H surface. J. Phys.-Condes. Matter. 24(9), 1–13 (2012). https://doi.org/10.1088/0953-8984/24/9/095011

    Article  Google Scholar 

  12. Walus, K., Dysart, T.J., Jullien, G.A., Budiman, R.A.: QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata. IEEE Trans. Nanotechnol. 3(1), 26–31 (2004). https://doi.org/10.1109/TNANO.2003.820815

    Article  ADS  Google Scholar 

  13. Navi, K., Farazkish, R., Sayedsalehi, S., Rahimi Azghadi, M.: A new quantum-dot cellular automata full-adder. Microelectron. J. 41(12), 820–826 (2010). https://doi.org/10.1016/j.mejo.2010.07.003

    Article  Google Scholar 

  14. Chabi, A.M., Roohi, A., Khademolhosseini, H., Sheikhfaal, S., Angizi, S., Navi, K., DeMara, R.F.: Towards ultra-efficient QCA reversible circuits. Microprocess. Microsyst. 49, 127–138 (2017). https://doi.org/10.1016/j.micpro.2016.09.015

    Article  Google Scholar 

  15. Farazkish, R., Azghadi, M.R., Navi, K., Haghparast, M.: New method for decreasing the number of quantum dot cells in QCA circuits. World Appl. Sci. J. 4(6), 793–802 (2008)

    Google Scholar 

  16. Berarzadeh, M., Mohammadyan, S., Navi, K., Bagherzadeh, N.: A novel low power exclusive-OR via cell level-based design function in quantum cellular automata. J. Comput. Electron. 16(3), 875–882 (2017). https://doi.org/10.1007/s10825-017-0986-7

    Article  Google Scholar 

  17. Momenzadeh, M., Huang, J., Tahoori, M.B., Lombardi, F.: Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12), 1881–1892 (2005). https://doi.org/10.1109/TCAD.2005.852667

    Article  Google Scholar 

  18. Zhang, R., Walus, K., Wang, W., Jullien, G.A.: A method of majority logic reduction for quantum cellular automata. IEEE Trans. Nanotechnol. 3(4), 443–450 (2004). https://doi.org/10.1109/TNANO.2004.834177

    Article  ADS  Google Scholar 

  19. Zhang, R., Gupta, P., Jha, N.K.: Majority and minority network synthesis with application to QCA-, SET-, and TPL-based nanotechnologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7), 1233–1245 (2007). https://doi.org/10.1109/TCAD.2006.888267

    Article  Google Scholar 

  20. Kong, K., Shang, Y., Lu, R.: An optimized majority logic synthesis methodology for quantum-dot cellular automata. IEEE Trans. Nanotechnol. 9(2), 170–183 (2010). https://doi.org/10.1109/TNANO.2009.2028609

    Article  ADS  Google Scholar 

  21. Wang, P., Niamat, M.Y., Vemuru, S.R., Alam, M., Killian, T.: Synthesis of majority/minority logic networks. IEEE Trans. Nanotechnol. 14(3), 473–483 (2015). https://doi.org/10.1109/TNANO.2015.2408330

    Article  ADS  Google Scholar 

  22. Soeken, M., Amaru, L.G., Gaillardon, P.E., De Micheli, G.: Exact synthesis of majority-inverter graphs and its applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(11), 1842–1855 (2017). https://doi.org/10.1109/tcad.2017.2664059

    Article  Google Scholar 

  23. Abedi, D., Jaberipur, G.: Decimal full adders specially designed for quantum-dot cellular automata. IEEE Trans. Circuits Syst. II Express Briefs. 65(1), 106–110 (2018). https://doi.org/10.1109/TCSII.2017.2703942

    Article  Google Scholar 

  24. Perri, S., Corsonello, P., Cocorullo, G.: Area-delay efficient binary adders in QCA. IEEE Trans. Very Large Scale Integr. VLSI Syst. 22(5), 1174–1179 (2014). https://doi.org/10.1109/TVLSI.2013.2261831

    Article  Google Scholar 

  25. Kianpour, M., Sabbaghi-Nadooshan, R.: A novel quantum-dot cellular automata X-bit × 32-bit SRAM. IEEE Trans. Very Large Scale Integr. VLSI Syst. 24(3), 827–836 (2016). https://doi.org/10.1109/TVLSI.2015.2418278

    Article  MATH  Google Scholar 

  26. Taskin, B., Hong, B.: Improving line-based QCA memory cell design through dual phase clocking. IEEE Trans. Very Large Scale Integr. VLSI Syst. 16(12), 1648–1656 (2008). https://doi.org/10.1109/TVLSI.2008.2003171

    Article  Google Scholar 

  27. Mustafa, M., Beigh, M.R.: Design and implementation of quantum cellular automata based novel parity generator and checker circuits with minimum complexity and cell count. Indian J. Pure Appl. Phys. 51(1), 60–66 (2013). https://doi.org/10.1140/epjh/e2012-30008-3

    Article  Google Scholar 

  28. Kianpour, M., Sabbaghi-Nadooshan, R., Navi, K.: A novel design of 8-bit adder/subtractor by quantum-dot cellular automata. J. Comput. Syst. Sci. 80(7), 1404–1414 (2014). https://doi.org/10.1016/j.jcss.2014.04.012

    Article  MathSciNet  MATH  Google Scholar 

  29. Khosroshahy, M.B., Moaiyeri, M.H., Angizi, S., Bagherzadeh, N., Navi, K.: Quantum-dot cellular automata circuits with reduced external fixed inputs. Microprocess. Microsyst. 50, 154–163 (2017). https://doi.org/10.1016/j.micpro.2017.03.009

    Article  Google Scholar 

  30. Singh, G., Sarin, R.K., Raj, B.: A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis. J. Comput. Electron. 15(2), 455–465 (2016). https://doi.org/10.1007/s10825-016-0804-7

    Article  Google Scholar 

  31. Angizi, S., Alkaldy, E., Bagherzadeh, N., Navi, K.: Novel robust single layer wire crossing approach for exclusive OR sum of products logic design with quantum-dot cellular automata. J. Low Power Electron. 10(2), 259–271 (2014). https://doi.org/10.1166/jolpe.2014.1320

    Article  Google Scholar 

  32. Sasamal, T.N., Ghanekar, U., Singh, A.K.: Design and analysis of ultra-low power QCA parity generator circuit. In: Garg, A., Bhoi, A., Sanjeevikumar, P., Kamani, K. (eds.) Lecture Notes in Electrical Engineering, vol. 436, pp. 347–354. Springer, Singapore (2018)

    Google Scholar 

  33. Sheikhfaal, S., Angizi, S., Sarmadi, S., Moaiyeri, M.H., Sayedsalehi, S.: Designing efficient QCA logical circuits with power dissipation analysis. Microelectron. J. 46(6), 462–471 (2015). https://doi.org/10.1016/j.mejo.2015.03.016

    Article  Google Scholar 

  34. Mohammadi, H., Navi, K.: Energy-efficient single-layer QCA logical circuits based on a novel XOR gate. J. Circuits Syst. Comput. (2018). https://doi.org/10.1142/S021812661850216X

    Article  Google Scholar 

  35. Poorhosseini, M., Hejazi, A.R.: A fault-tolerant and efficient XOR structure for modular design of complex QCA circuits. J. Circuits Syst. Comput. 27(7), 1–24 (2017). https://doi.org/10.1142/S0218126618501153

    Article  Google Scholar 

  36. Chaudhary, A., Chen, D.Z., Hu, X.S., Whitton, K., Niemier, M., Ravichandran, R.: Eliminating wire crossings for molecular quantum-dot cellular automata implementation. In: ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005, San Jose, 6–10 Nov. 2005, pp. 565–571. IEEE

  37. Chung, W.J., Smith, B., Lim, S.K.: QCA physical design with crossing minimization. In: 5th IEEE conference on nanotechnology, 2005, Nagoya, 15–15 July 2005, pp. 108–111. IEEE

  38. Smith, B.S., Lim, S.K.: QCA channel routing with wire crossing minimization. In: 2005 ACM Great Lakes symposium on VLSI, GLSVLSI'05, Chicago, IL, United states, April 17–19, 2005 2005. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, pp. 217–220. Association for Computing Machinery

  39. Krishnaswamy, S., Viamontes, G.F., Markov, I.L., Hayes, J.P.: Probabilistic transfer matrices in symbolic reliability analysis of logic circuits. ACM Trans. Des. Autom. Electron. Syst. 13(1), 1–8 (2008). https://doi.org/10.1145/1297666.1297674

    Article  Google Scholar 

  40. Srivastava, S., Sarkar, S., Bhanja, S.: Estimation of upper bound of power dissipation in QCA circuits. IEEE Trans. Nanotechnol. 8(1), 116–127 (2009). https://doi.org/10.1109/TNANO.2008.2005408

    Article  ADS  Google Scholar 

  41. Liu, W., Lu, L., Oneill, M., Swartzlander, E.E.: A first step toward cost functions for quantum-dot cellular automata designs. IEEE Trans. Nanotechnol. 13(3), 476–487 (2014). https://doi.org/10.1109/TNANO.2014.2306754

    Article  ADS  Google Scholar 

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Acknowledgements

This work is supported by the Fundamental Research Funds for the Central Universities of China (No. JZ2019HGTB0092).

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Correspondence to Guangjun Xie.

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Zhang, Y., Deng, F., Cheng, X. et al. A Coplanar XOR Using NAND-NOR-Inverter and Five-Input Majority Voter in Quantum-Dot Cellular Automata Technology. Int J Theor Phys 59, 484–501 (2020). https://doi.org/10.1007/s10773-019-04343-w

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