Skip to main content
SpringerLink
Log in

The Length of Single Fault Detection Tests with Respect to Substitution of Gates with Inverters

  • Published:
Computational Mathematics and Modeling Aims and scope Submit manuscript

We show that for an arbitrary Boolean function realized by a combinational circuit over an arbitrary com-plete basis, there exists an irredundant circuit that admits a single fault detection test with at most 12 tuples with respect to substitutions of gates with inverters.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. V. Geetha, N. Devarajan, and P. N. Neelakantan, “AAnalysis of different types of faults in a class of Boolean circuits,” International Journal of Engineering and Innovative Technology, 2, No. 4, 145–149 (2012).

    Google Scholar 

  2. V. Geetha, N. Devarajan, and P. N. Neelakantan, “Single network structure for stuck-at and bridging fault analysis and diagnosis for Exclusive-OR sum of products in Reed–Muller canonical circuits,” Elixir Elec. Eng., 57, 14080–14085 (2013).

  3. V. Geetha, N. Devarajan, and P. N. Neelakantan, “Network structure for testability improvement in exclusive-OR sum of products Reed–Muller canonical circuits,” Int. J. Eng. Res. Gen. Sci., 3, No. 3, 368–378 (2015).

  4. A. K. Jameil, “A new single stuck fault detection algorithm for digital circuits,” Int. J. Eng. Res. Gen. Sci., 3, No. 1, 1050–1056 (2015).

    Google Scholar 

  5. S. M. Reddy, “Easily testable realization for logic functions,” IEEE Trans. Comput., 21, No. 1, 124–141 (1972).

    MathSciNet  Google Scholar 

  6. S. M. Thamarai, K. Kuppusamy, and T. Meyyappan, “Fault detection and test minimization methods for combinational circuits — a survey,” International Journal of Computer Trends and Technology, 2, No. 2, 140–146 (2011).

    Google Scholar 

  7. Yu. V. Borodina, “Synthesis of easily-tested circuits in the case of single-type constant malfunctions at the element outputs,” Moscow University Computational Mathematics and Cybernetics, 32, No. 1, 42–46 (2008); DOI: https://doi.org/10.3103/S0278641908010068.

    Article  MathSciNet  MATH  Google Scholar 

  8. Yu. V. Borodina, “Circuits admitting single-fault tests of length 1 under constant faults at outputs of elements,” Moscow University Mathematics Bulletin, 63, No. 5, 202–204 (2008); DOI: https://doi.org/10.3103/S0027132208050069.

    Article  MathSciNet  MATH  Google Scholar 

  9. Yu. V. Borodina and P. A. Borodin, “Synthesis of easily testable circuits over the Zhegalkin basis in the case of constant faults of type 0 at outputs of elements,” Discr. Math., 20, No. 4, 441–449 (2010); DOI: https://doi.org/10.1515/dma.2010.027.

    Article  MATH  Google Scholar 

  10. S. V. Kovatsenko, “SSynthesis of easily testable circuits in the Zhegalking basis for inversion faults,” Vestnik MGU, Ser. 15: Vychisl. Matem. i Kibern., No. 2, 45–47 (2000).

  11. S. S. Kolyada, “Unit checking output tests under constant faults for functional elements,” Moscow Univ. Math. Bull., 66, 267–269 (2011); DOI: https://doi.org/10.3103/S002713221106009X.

    Article  MathSciNet  MATH  Google Scholar 

  12. S. S. Kolyada, “Single-fault detection tests for combinational circuits in bases of elements with at most two inputs,” Diskr. Analiz Issled. Operatsii, 20, No. 2, 58–74 (2013).

    MathSciNet  Google Scholar 

  13. S. S. Kolyada, “Single fault detection tests for circuits of functional elements,” Moscow Univ. Math. Bull., 68, 192–193 (2013); DOI: https://doi.org/10.3103/S0027132213040049.

    Article  MathSciNet  MATH  Google Scholar 

  14. K. A. Popkov, “Lower bounds for lengths of single tests for Boolean circuits,” Discrete Mathematics and Applications, 29, No. 1, 23–33 (2019); DOI: 10.1515/dma-2019–0004.

  15. K. A. Popkov, “Single-fault detection tests for combinational circuits in the “and-not” basis,” Prikl. Diskr. Matem., 38, 66–88 (2017).

    Article  Google Scholar 

  16. K. A. Popkov, “Short single tests for circuits with arbitrary stuck-at faults at outputs of gates,” Discrete Mathematics and Applications, 29, No. 5, 321–333 (2019); DOI: https://doi.org/10.1515/dma-2019-0030.

    Article  MathSciNet  MATH  Google Scholar 

  17. K. A. Popkov, “On circuits admitting short single fault detection tests for arbitrary gate faults,” Prikl. Diskr. Matem., No. 51, 85–100 (2021).

    MATH  Google Scholar 

  18. N. P. Red’kin, “On complete fault detection tests for combinational circuits,” Matem. Voprosy Kibern., Nauka, Moscow, No. 2, 198–222 (1989).

  19. N. P. Red’kin, Reliability and Circuit Diagnosis [in Russian], Izd. MGU, Moscow (1992).

  20. N. P. Red’kin, “Single fault detection tests for circuits with inversion faults,” Matem. Voprosy Kibern., Fizmatlit, Moscow, No. 12, 217–230 (2003).

  21. D. S. Romanov, “Method of synthesis of easily testable circuits admitting single fault detection tests of constant length,” Discrete Mathematics and Applications, 24, No. 4, 227–251 (2014); DOI: https://doi.org/10.1515/dma-2014-0021.

    Article  MathSciNet  MATH  Google Scholar 

  22. D. S. Romanov and E. Yu. Romanova, “A method of synthesis of irredundant circuits admitting single fault detection tests of constant length,” Discrete Mathematics and Applications, 29, No. 1, 35–48 (2019); DOI: https://doi.org/10.1515/dma-2019-0005.

    Article  MathSciNet  MATH  Google Scholar 

  23. G. G. Temerbekova and D. S. Romanov, “On single fault detection tests with respect to gate-inverter replacements,” Uchenye Zapiski Kazan Univ., Ser. Phys.-Math. Sci., 162, No. 3, 359–366 (2020).

    Google Scholar 

  24. G. G. Temerbekova and D. S. Romanov, “The length of single fault detection tests with respect to gate-inverter replacements in some bases,” Prikl. Matem. Informat., MAKS Press, Moscow, No. 67, 89–100 (2021); English translation: “On single detection test sets under replacements of gates with inverters in some bases,” Computational Mathematics and Modeling, 32, No. 3, pp. 356–363 (2021).

Download references

Author information

Authors and Affiliations

  1. Faculty of Computational Mathematics and Cybernetics, Lomonosov Moscow State University, Moscow, Russia

    G. Temerbekova & D. S. Romanov

Authors
  1. G. Temerbekova
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. D. S. Romanov
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to G. Temerbekova.

Additional information

Translated from Prikladnaya Matematika i Informatika, No. 68, 2021, pp. 97–110.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Temerbekova, G., Romanov, D.S. The Length of Single Fault Detection Tests with Respect to Substitution of Gates with Inverters. Comput Math Model 32, 505–513 (2021). https://doi.org/10.1007/s10598-022-09550-5

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10598-022-09550-5

Keywords

Search

Navigation