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Novel nonlinearity minimized time-to-digital converters with digital calibration technique

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Abstract

This paper presents a low nonlinearity, four channel Gated Ring Oscillator (GRO) based Time-to-Digital Converters (TDC) in Xilinx 28 nm Virtex 7 Field Programmable Gate Arrays. Gray code counter provides a coarse time measurement value, and the fine residue information is obtained from the 64 stages of sampling registers outputs. GRO based TDC places the carry logics as a delay element in a ring topology such that it can be reused for measuring large time intervals. Online calibration by the code density analysis is implemented to minimize linearity errors. After calibration and normalization, the proposed architecture has achieved an improved Differential Non-linearity in the range of [− 0.12, 0.11] LSB, and Integral Non-linearity in the range of [− 0.2, 0.4] LSB. The proposed architecture is also cost effective in terms of resource consumption with a high resolution of 15 ps.

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Data availability

All data generated or analyzed in this article are obtained based on simulation result of the circuit with different clock signals. The datasets generated are not publicly available. The proposed architecture is simulated with random inputs and values are presented in figures.

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Authors and Affiliations

  1. R.M.K. Engineering College, Gummidipoondi, TamilNadu, India

    P. Latha

  2. Vellore Institute of Technology, Vellore, TamilNadu, India

    R. Sivakumar

  3. Anna University, Chennai, TamilNadu, India

    Y. V. Ramana Rao

  4. University of Saskatchewan, Saskatchewan, Saskatoon, Canada

    Seok-Bum Ko

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  1. P. Latha
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  2. R. Sivakumar
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  4. Seok-Bum Ko
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Latha, P., Sivakumar, R., Rao, Y.V.R. et al. Novel nonlinearity minimized time-to-digital converters with digital calibration technique. Analog Integr Circ Sig Process 113, 9–25 (2022). https://doi.org/10.1007/s10470-022-02065-4

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  • DOI: https://doi.org/10.1007/s10470-022-02065-4

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