TSPC-HNTL: True Single Phase Clock technique for High speed, Noise Tolerance, and Low power

Abstract

Stupendous and inevitable applications of dynamic CMOS circuits add thrust to its optimization to high-end performance. Dynamic logic circuits are very efficient in terms of speed, but these circuits suffer from high power consumption and noise. A high-speed circuit with low power consumption and high robustness is required with recent advancements. It has become necessary to find a circuit design technique that can utilize the features of dynamic logic and provide ways to overcome its drawbacks. The proposed technique is named TSPC-HNTL (True Single Phase Clock technique for High speed, Noise Tolerance, and Low Power). In this approach, the threshold voltage of specifically selected two transistors in the pull-down network is regulated meticulously through the proposed threshold voltage tuning circuit. The bias tuner circuit provides forward body biasing during the active mode of operation to achieve high-speed operation and reverse body biasing during the standby mode of operation to achieve low power consumption and noise. Further, a transistor is placed in a pull-up network to provide a stacking effect. This stacking transistor is connected with a gate tied to the drain terminal. The proposed design technique is thoroughly studied and analyzed for all performance parameters such as power delay product, leakage power consumption, process corner analysis, unity noise gain, ground/supply bounce noise, sizing, etc. An appreciable reduction in power delay product is achieved with the proposed design technique. The proposed design is also having higher unity noise gain and reduced voltage bouncing noise as compared to other design techniques. It is found to be robust with temperature, voltage, sizing, and process corner variations. It is found that the proposed TSPC-HNTL dynamic circuit design technique is a better performer in-class for every parameter of performance evaluation.