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Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications

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Abstract

Physically unclonable functions (PUF) are digital fingerprints which generate high entropy, temper-resilient keys and/or chip-identifiers for security applications. When considering the miniaturized hardware development for the Internet of Things (IoT), security is of high importance. In this case, PUF designing using SRAM or D flip-flops are quite common but with compromised uniqueness due to the limited silicon area. In this work, a symmetric tri-state D flip-flop based lightweight PUF is proposed with increased uniqueness. The proposed architecture is implemented using a standard 40 nm CMOS technology. The post-layout simulation results show that it offers a uniqueness of 0.4994, which is the highest among all the considered architectures. Compared to the Arbiter PUF the proposed architecture has 0.267 \(\times\), 0.064 \(\times\), and 0.043 \(\times\) less, power, silicon area, and energy per bit, respectively. Similarly, when compared with the Ring Oscillator PUF, the proposed architecture has 0.017 \(\times\), 0.031 \(\times\), and 0.0005 \(\times\) less, power, silicon area, and energy per bit, respectively. Also, unlike other flip-flop based PUF, the proposed one does not require any post-processing block to remove the bias, thus contributes to saving the total implementation area and power of the system. An FPGA implementation is also presented as a proof-of-concept to verify functional correctness. For a better performance comparison among the considered architectures, a novel figure of merit (FOM) considering power, reliability, delay, silicon area, and uniqueness has been proposed, and it is observed that the proposed architecture offers the highest FOM among considered PUF architectures.

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Acknowledgements

The authors would like to thank the UGC, Government of India under the JRF Scheme for providing financial support (Ref. No. 3548/NET-DEC. 2015). We also extend our sincere gratitude to SMDP-C2SD program of the Government of India.

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Authors and Affiliations

  1. Indian Institute of Technology Indore, Indore, MP, 453552, India

    Sajid Khan, Sudha Rani, Neha Gupta & Santosh Kumar Vishvakarma

  2. Institute for Microelectronics, Technische Universität Wien, 1040, Vienna, Austria

    Ambika Prasad Shah

  3. EIS Lab, Department of Computer Science, Electrical and Space Engineering, Lulea University of Technology, 97187, Luleå, Sweden

    Shailesh Singh Chouhan

  4. Integrated System Group, CSIR-CEERI, Pilani, Rajasthan, 333031, India

    Jai Gopal Pandey

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  1. Sajid Khan
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Correspondence to Santosh Kumar Vishvakarma.

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Khan, S., Shah, A.P., Chouhan, S.S. et al. Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications. Analog Integr Circ Sig Process 103, 477–492 (2020). https://doi.org/10.1007/s10470-020-01642-9

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