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Design-to-testing: a low-power, 1.25 GHz, single-bit single-loop continuous-time \(\Delta \Sigma\) modulator with 15 MHz bandwidth and 60 dB dynamic range

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Abstract

Continuous-time Delta-Sigma (CT-\(\Delta \Sigma\)) analog-to-digital converters have been extensively investigated for their use in wireless receivers to achieve conversion bandwidths >15 MHz and higher resolution of 10–14 bits. This paper presents the complete design-to-testing tutorial of a state-of-the-art high-speed single-bit CT-\(\Delta \Sigma\) architecture and its circuit design details in 0.13 μm CMOS technology node sampling at 1.25 GS/s. The designed modulator achieves higher dynamic range of 60 dB in a wide conversion bandwidth of 15 MHz and consumes only 3.5 mW. The proposed modulator achieves a Figure of Merit of 154 fJ/level.

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References

  1. Fettweis, G., & Zimmermann, E. (2008). ICT energy consumption-trends and challenges. In Proceedings of the 11th international symposium on wireless personal multimedia communications (Vol. 2, No. 4, p. 6).

  2. Balagopal, S. (2014). High-speed delta-sigma data converters for next-generation wireless communication. Ph.D. dissertation, Boise State University.

  3. Razavi, B., Aytur, T., Lam, C., Yang, F., Yan, R., Kang, H., et al. (2005). Multiband UWB transceivers. In Proceedings of the IEEE custom integrated circuits conference, 2005. (pp. 141–148). IEEE.

  4. Schreier, R., & Temes, G. (2005). Understanding delta-sigma data converters. Piscataway, NJ: IEEE Press.

    Google Scholar 

  5. Ortmanns, M., & Gerfers, F. (2006). Continuous-time sigma-delta A/D conversion: Fundamentals, performance limits and robust implementations (Vol. 21). Berlin: Springer.

    Google Scholar 

  6. De Maeyer, J., Raman, J., Rombouts, P., & Weyten, L. (2005). Controlled behaviour of STF in CT \(\Sigma \Delta\) modulators. Electronics Letters, 41, 896.

    Article  Google Scholar 

  7. Bolatkale, M., Breems, L. J., Rutten, R., & Makinwa, K. A. (2011). A 4 GHz CT \(\Delta \Sigma\) ADC with 70 dB DR and-74 dBFS THD in 125 MHz BW. In ISSCC digital technical papers (pp. 470–471).

  8. Galton, I. (2002). Delta-sigma data conversion in wireless transceivers. IEEE Transactions on Microwave Theory and Techniques, 50(1), 302–315.

    Article  Google Scholar 

  9. Balagopal, S., Koppula, R., Saxena, V. (2011). Systematic design of multi-bit continuous-time delta-sigma modulators using two-step quantizer. In IEEE 54th international midwest symposium on circuits and systems (MWSCAS) (pp. 1–4). IEEE.

  10. Koppula, R. M. R., Balagopal, S., Saxena, V. (2012). Multi-bit continuous-time delta-sigma modulator for audio application. In IEEE workshop on microelectronics and electron devices (pp. 1–5). IEEE.

  11. Pavan, S., Krishnapura, N., Pandarinathan, R., & Sankar, P. (2008). A power optimized continuous-time \(\Sigma \Delta\) ADC for audio applications. IEEE Journal of Solid-State Circuits, 43(2), 351–360.

    Article  Google Scholar 

  12. Reddy, K., Pavan, S. (2008). A 20.7 mW continuous-time \(\Delta \Sigma\) modulator with 15 MHz bandwidth and 70 dB dynamic range. In 34th European solid-state circuits conference, ESSCIRC 2008 (pp. 210–213). IEEE.

  13. Balagopal, S., Zhu, K., & Saxena, V. (2014). A 1 gs/s, 31 mhz bw, 76.3 db dynamic range, 34 mw ct-\(\delta \sigma\) upsigma adc with 1.5 cycle quantizer delay and improved stf. Analog Integrated Circuits and Signal Processing, 78(2), 275–286.

    Article  Google Scholar 

  14. Murmann, B. (2010). ADC performance survey 1997–2010,” Online, June, 2010.

  15. Mitteregger, G., Ebner, C., Mechnig, S., Blon, T., Holuigue, C., & Romani, E. (2006). A 20-mW 640-MHz CMOS continuous-time \(\Sigma \Delta\) ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB. IEEE Journal of Solid-State Circuits, 41(12), 2641–2649.

    Article  Google Scholar 

  16. Kauffman, J., Witte, P., Becker, J., Ortmanns, M. (2011). An 8 mW 50MS, s CT \(\Delta \Sigma\) modulator with 81 dB SFDR and digital background DAC linearization. In IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 472–474). IEEE.

  17. Balagopal, S., Roy, R., Saxena, V. (2010). A 110 μW single-bit continuous-time \(\Delta \Sigma\) converter with 92.5 dB dynamic range. In IEEE Dallas circuits and systems Workshop (DCAS) (pp. 1–4). IEEE.

  18. Lee, W. L. (1987). A novel higher order interpolative modulator topology for high resolution oversampling A/D converters. Ph. D. Thesis, Massachusetts Institute of Technology.

  19. Munoz, F., Philips, K., Torralba, A. (2005). A 4.7 mW 89.5 dB DR CT complex \(\Delta \Sigma\) ADC with built-in LPF. In IEEE international solid-state circuits conference, digest of technical papers, ISSCC, 2005 (pp. 500–613). IEEE.

  20. Balagopal, S., & Saxena, V. (2012). Design of wideband continuous-time \(\Delta \Sigma\)fs ADCs using two-step quantizers. In (invited) proceedings of 55th international midwest symposium on circuits and systems (MWSCAS), Boise.

  21. Reddy, K., & Pavan, S. (2007). Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter. IEEE Transactions on Circuits and Systems I: Regular Papers, 54(10), 2184–2194.

    Article  Google Scholar 

  22. Razavi, B. (1995). Principles of data converter system design. New York: Wiley.

    Google Scholar 

  23. Gustavsson, M., Wikner, J. J., & Tan, N. (2000). CMOS data converters for communications. Berlin: Springer.

    Google Scholar 

  24. Pavan, S. (2011). Alias rejection of continuous-time delta sigma modulators with switched-capacitor feedback DACs. IEEE Transactions on Circuits and Systems I-Regular Papers, 58(2), 233–243.

    Article  MathSciNet  Google Scholar 

  25. Chen, X. (2007). A wideband low-power continuous-time delta-sigma modulator for next generation wireless applications. Ph.D. dissertation.

  26. Balagopal, S., & Saxena, V. (2012). A low-power single-bit continuous-time \(\delta \sigma\) converter with 92.5 db dynamic range for biomedical applications. Journal of Low Power Electronics and Applications, 2(3), 197–209.

    Article  Google Scholar 

  27. Ranjbar, M. (2012). Power efficient continuous-time delta-sigma modulator architectures for wideband analog to digital conversion. Ph.D. dissertation.

  28. Balagopal, S., Zhu, K., Saxena, V. (2013). Systematic synthesis of cascaded continuous-time \(\delta \sigma\) adcs for wideband data conversion. In IEEE 56th international midwest symposium on circuits and systems (MWSCAS) (pp. 860–863). IEEE.

  29. Thandri, B. K., & Silva-Martínez, J. (2003). A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors. IEEE Journal of Solid-State Circuits, 38(2), 237–243.

    Article  Google Scholar 

  30. Schinkel, D., Mensink, E., Kiumperink, E., Van Tuijl, E., Nauta, B. (2007). A double-tail latch-type voltage sense amplifier with 18ps setup+ hold time. In IEEE international solid-state circuits conference, ISSCC 2007. Digest of Technical Papers (pp. 314–605). IEEE.

  31. Nikolic, B., Oklobdzija, V. G., Stojanovic, V., Jia, W., Chiu, J. K.-S., & Leung, M. Ming-Tak. (2000). Improved sense-amplifier-based flip-flop: Design and measurements. IEEE Journal of Solid-State Circuits, 35(6), 876–884.

    Article  Google Scholar 

  32. Jain, A., Venkateswaran, M., Pavan, S. (2011). A 4 mW 1 GS, s continuous-time \(\Delta \Sigma\) modulator with 15.6 MHz bandwidth and 67 dB dynamic range. In Proceedings of the ESSCIRC (ESSCIRC) (pp. 259–262). IEEE.

  33. Crombez, P., Van der Plas, G., Steyaert, M. S., & Craninckx, J. (2010). A single-bit 500 kHz-10 MHz multimode power-performance scalable 83-to-67 dB DR CT\(\Delta \Sigma\) for SDR in 90 nm digital CMOS. IEEE Journal of Solid-State Circuits, 45(6), 1159–1171.

    Article  Google Scholar 

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Authors and Affiliations

  1. Boise state university, Boise, ID, USA

    Sakkarapani Balagopal, Kehan Zhu, Xinyu Wu & Vishal Saxena

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  1. Sakkarapani Balagopal
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  2. Kehan Zhu
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  3. Xinyu Wu
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  4. Vishal Saxena
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Correspondence to Sakkarapani Balagopal.

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Balagopal, S., Zhu, K., Wu, X. et al. Design-to-testing: a low-power, 1.25 GHz, single-bit single-loop continuous-time \(\Delta \Sigma\) modulator with 15 MHz bandwidth and 60 dB dynamic range. Analog Integr Circ Sig Process 90, 625–638 (2017). https://doi.org/10.1007/s10470-016-0865-3

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  • DOI: https://doi.org/10.1007/s10470-016-0865-3

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