Abstract
An all-digital phase locked loop (ADPLL) taking new approach for design of the loop filter is presented. A feedback loop in the time domain by modeling the DCO and TDC as an appropriate model in the state-space form is proposed. Then, a model predictive control (MPC) method for designing loop filter in order to generate an optimal control signal is employed. The proposed loop filter can overcome latency issue that inevitably exists in most of digital systems. Furthermore, the proposed MPC loop filter achieves rapid transient response time and enables us to model other noise sources resulted from oscillator pulling and flicker noise which are common problems in many modern transceivers and the effects of which can be dramatically removed without degrading the overall phase noise performance. Simulation results confirm the capability of the proposed design and show it is significantly more robustness against these problems compared to conventional digital PLL.
Similar content being viewed by others
References
Gardner, F. M. (2005). Phaselock techniques (3rd ed.). Hoboken: Wiley.
Hwang, I.-C., Song, S.-H., & Kim, S.-W. (2001). A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition. IEEE Journal of Solid-State Circuits, 36(10), 1574–1581.
Lin, J., Haroun, B., Foo, T., Helmick, B., Randall, S., Mayhugh, T., Barr, C., & Kirkpatric, J. (2004). A PVT tolerant 0.18 MHz to 600 MHz self-calibrated digital PLL in 90 nm CMOS process. In 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No. 04CH37519), pp. 488–541.
Ho, Y.-H., & Yao, C.-Y. (2016). A low-jitter fast-locked all-digital phase-locked loop with phase–frequency-error compensation. IEEE Transaction on Very Large Scale Integration Systems, 24(5), 1984–1992.
Staszewski, R. B., Wallberg, J., Rezeq, S., Eliezer, O., Vemulapalli, S., Staszewski, R., et al. (2005). All-digital PLL and GSM, edge transmitter in 90 nm CMOS”, in ISSCC. IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005(2005), 316–318.
Staszewski, R. B., Fernando, C., & Balsara, P. T. (2005). Event-driven simulation and modeling of phase noise of an RF oscillator. IEEE Transactions on Circuits and Systems I: Regular Papers, 52(4), 723–733.
Kratyuk, V., Hanumolu, P. K., Ok, K., & Mayaram, K. (2009). A digital PLL with a stochastic time-to-digital converter. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(8), 1612–1621.
Wu, W., Staszewski, R. B., & Long, J. R. (2014). A 56.4-to-63.4 GHz multi-rate all-digital fractional-N PLL for FMCW radar applications in 65 nm CMOS. IEEE Journal of Solid-State Circuits, 49(5), 1081–1096.
Razavi, B. (1996). Monolithic phase-locked loops and clock recovery circuits. New York: IEEE Press.
Razavi, B. (2004). A study of injection locking and pulling in oscillators. IEEE Journal of Solid-State Circuits, 39(9), 1415–1424.
Namgoong, W. (2010). Observer-controller digital PLL. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(3), 631–641.
Mendel, S., & Vogel, C. (2007). A z-domain model and analysis of phase-domain all-digital phase-locked loops. Norchip, 2007, 1–6.
Bergmans, J. W. M. (2005). Effect of loop delay on phase margin of first-order and second-order control loops. IEEE Transactions on Circuits and Systems II: Express Briefs, 52(10), 621–625.
Staszewski, R. B., & Balsara, P. T. (2006). All-digital frequency synthesizer in deep-submicron CMOS. Hoboken, NJ: Wiley.
Mendel, S., Vogel, C., & Da Dalt, N. (2009). Mixed design of integrated circuits & systems, 2009. In MIXDES’09. MIXDES-16th International Conference, pp. 681–687.
Mendel, S., Vogel, C., & Da Dalt, N. (2009). A phase-domain all-digital phase-locked loop architecture without reference clock retiming. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(11), 860–864.
Mendel, S., & Vogel, C. (2008). Improved lock-time in all-digital phase-locked loops due to binary search acquisition. In 2008 15th IEEE International Conference on Electronics, Circuits and Systems, pp. 384–387.
Namgoong, W. (2016). An all-digital approach to supply noise cancellation in digital phase-locked loop. IEEE Transaction on Very Large Scale Integration Systems, 24(3), 1025–1035.
Bolognani, S., Peretti, L., & Zigliotto, M. (2009). Design and implementation of model predictive control for electrical motor drives. IEEE Transactions on Industrial Electronics, 56(6), 1925–1936.
Kwon, W. H., Han, S., & Han, S. H. (2005). Receding horizon control: Model predictive control for state models. London: Springer.
Landau, I. D., Lozano, R., M’Saad, M., & Karimi, A. (2011). Adaptive control: Algorithms, analysis and applications. New York: Springer.
Wang, L. (2009). Model predictive control system design and implementation using MATLAB ®. London: Springer.
Löfberg, J. (2003). Minimax approaches to robust model predictive control. Linköping: Linköping University Electronic Press.
Hartley, E. N., & Maciejowski, J. M. (2011). Designing MPC controllers by reverse-engineering existing LTI controllers.
Ogata, K. (2002). Modern control engineering (Vol. 17). Boca Raton: CRC Press.
Sayadi, M., Farshidi, E., & Ghaffari, V. (2012). A fast digital phase locked loop based on model predictive controller. In 20th Iranian Conference on Electrical Engineering (ICEE2012), pp. 65–69.
Knagge, G., Wills, A., Mills, A., & Ninness, B. (2009). ASIC and FPGA implementation strategies for model predictive control. In European Control Conference ECC 2009.
Agarwal, V., Gupta, M., Gupta, U., & Saraswat, R. (2014). A model predictive controller using multiple linear models for continuous stirred tank reactor (CSTR) and ITS implementation issue. In Communication Systems and Network Technologies (CSNT), 2014 Fourth International Conference on, no. 1, pp. 1001–1005.
Adler, R. (1973). Study of locking phenomena in oscillators. Proceedings of the IEEE, 61(10), 1380–1385.
Razavi, B. (2004). A study of injection locking and pulling in oscillators. IEEE Journal of Solid-State Circuits, 39(9), 1415–1424.
Namgoong, Won. (2010). Flicker noise in observer-controller digital PLL. IEEE Transactions on Circuits and Systems II: Express Briefs, 57(7), 556–560.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Sayadi, M., Farshidi, E. A fast locked and low phase noise all-digital phase locked loop based on model predictive control. Analog Integr Circ Sig Process 88, 401–414 (2016). https://doi.org/10.1007/s10470-016-0794-1
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-016-0794-1