Abstract
We propose here an analytical model for proportional–integral–derivative controlled phase-locked loop for communication systems. The transfer function of the system has been derived and simulated to analyze the various aspects, e.g. settling time, phase margin, damping factor, overshoot, bandwidth and stability of the system. From the analysis of simulation results it is observed that the settling time of the system decreases exponentially with increasing phase margin and it increases exponentially with increasing damping factor. It is also observed that the settling time and percentage of overshoot of the system is inversely proportional to each other. The settling time is also decreased exponentially with the increase in bandwidth. The Bode plot and Root Locus analysis show that the proposed system is highly stable. The system provides a fastest settling time of up to 238.57 ps. The system can also improve the settling time by 99.9% over the conventional system with a maximum frequency of 6.21802 GHz, which is the novelty of the proposed work.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Rahimpour H, Gholami M, Ardeshir G, MiarNaimi H (2015) Low settling time all digital DLL for VHF application. Int J Eng (IJE), Trans C: Asp 28(3):419–425. https://doi.org/10.5829/idosi.ije.2015.28.03c.11
Ali MKM, Hashemipour O (2019) Fast locking technique for phase locked loop based on phase error cancellation. AEU-Int J Electron Commun 109:99–106. https://doi.org/10.1016/j.aeue.2019.06.025
Nguyen NH, Nguyen PD (2018) Overshoot and settling time assignment with PID for first-order and second-order systems. IET Control Theory Appl 12(17):2407–2416. https://doi.org/10.1049/iet-cta.2018.5076
Golestan S, Mohammad M, Francisco DF, Josep MG (2014) Performance improvement of a prefiltered synchronous-reference-frame PLL by using a PID-type loop filter. IEEE Trans Ind Electron 61(7):3469–3479. https://doi.org/10.1109/TIE.2013.2282607
Yang WB, Wang HH, Chang HI, Lo YL (2020) A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications. Jpn J Appl Phys 59(SGGL08). https://doi.org/10.35848/1347-4065/ab7276
Shubin L, Sun D, Ding R, Huang S, Zhu Z (2019) A multiplexing DAPD technique for fast-locking and charge pumps calibration in PLLs. IEEE Microwave Wirel Compon Lett 29(8):535–537. https://doi.org/10.1109/LMWC.2019.2923891
Babu RSR, Deepa S, Jothivel SA (2014) Closed loop control of quadratic boost converter using PID controller. Int J Eng (IJE), Trans B: Appl 27(11):1653–1662. https://doi.org/10.5829/idosi.ije.2014.27.11b.02
Uyanik HU, Tarim N (2007) PID-controlled PLL for fast frequency-hopped systems. In: 6th IEEE Dallas circuits and systems workshop on system-on-chip, Dallas, TX, USA, pp 1–3. https://doi.org/10.1109/DCAS.2007.4433198
Konwar G, Bezboruah T (2008) Some aspects of modelling and simulation of a high frequency and fast settling time proportional-integral-derivative controlled phase-locked loop. In: 2018 2nd IEEE international conference on power, energy and environment: towards smart technology, pp 1–9. https://doi.org/10.1109/EPETSG.2018.8658754
Kuangand N, Wu X (2006) A fast-settling PLL frequency synthesizer with direct frequency presetting. In: IEEE international solid-state circuits conference, pp 741–750. https://doi.org/10.1109/ISSCC.2006.1696113
Ahmet K, Songuler O, Bogosyan S, Gokasan M (2012) Fast locking of PLLs using fuzzy scheduled SMC. In: 2012 IV IEEE international congress on ultra modern telecommunications and control systems, pp 234–239. https://doi.org/10.1109/ICUMT.2012.6459671
Sulaiman DR (2020) Novel high-frequency PLL design for wireless applications. J Electr Syst 16(3):332–349. http://journal.esrgroups.org/jes/papers/16_3_5.pdf
Beiraghdar F, Ghobadi RA, Sheikhaei S, Tohidian MA (2021) Fast settling frequency synthesizer with switched-bandwidth loop filter. Int J Circuit Theory Appl 49:2021–2031. https://doi.org/10.1002/cta.2993
Shanan H, Dalton D, Chillara V, Dato P (2022) A 9–12 GHz coupled-RTWO FMCW ADPLL with 97 fs RMS Jitter, −120 dBc/Hz PN at 1 MHz offset, and with retrace time of 12.5 ns and 2 μs chirp settling time. In: 2022 IEEE international solid-state circuits conference (ISSCC), pp 146–148. https://doi.org/10.1109/ISSCC42614.2022.9731575
Bertulessi L, Cherniak D, Mercandelli M, Samori C, Lacaita AL, Levantino S (2022) Novel feed-forward technique for digital bang–bang PLL to achieve fast lock and low phase noise. IEEE Trans Circuits Syst I: Regul Pap 69(5):1858–1870. https://doi.org/10.1109/TCSI.2022.3146788
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2023 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Konwar, G., Bezboruah, T. (2023). An Analytical Model for a Proportional–Integral–Derivative Controlled Phase-Locked Loop for Communication Systems. In: Borah, S., Gandhi, T.K., Piuri, V. (eds) Advanced Computational and Communication Paradigms . ICACCP 2023. Lecture Notes in Networks and Systems, vol 535. Springer, Singapore. https://doi.org/10.1007/978-981-99-4284-8_40
Download citation
DOI: https://doi.org/10.1007/978-981-99-4284-8_40
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-99-4283-1
Online ISBN: 978-981-99-4284-8
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)