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A high-resolution low-power and multi-bit incremental converter with smart-DEM

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Abstract

Alessandro.DAmato@ti.comThis paper describes a second-order 3-bit incremental converter, which employs a novel Smart-DEM algorithm to compensate for the mismatch among unity elements of the multi-level digital-to-analog converter. The design, which is fabricated in a mixed 0.18–0.5 \(\upmu\)m CMOS technology, achieves 16.7-bit resolution over a 5-kHz bandwidth by using 256 clock periods per sample. A single-step chopping technique leads to a residual offset of 9.7 \(\upmu\)V. The measured power consumption is 280 \(\upmu\)W and the achieved figure of merit is 174.95 dB.

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Authors and Affiliations

  1. Department of Electrical, Computer, and Biomedical Engineering, University of Pavia, Pavia, Italy

    Yao Liu, Edoardo Bonizzoni & Franco Maloberti

  2. SVA Precision Signal Path, Texas Instruments, Rozzano, MI, Italy

    Alessandro D’Amato

Authors
  1. Yao Liu
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  2. Edoardo Bonizzoni
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  3. Alessandro D’Amato
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  4. Franco Maloberti
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Correspondence to Edoardo Bonizzoni.

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Liu, Y., Bonizzoni, E., D’Amato, A. et al. A high-resolution low-power and multi-bit incremental converter with smart-DEM. Analog Integr Circ Sig Process 82, 663–674 (2015). https://doi.org/10.1007/s10470-015-0492-4

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  • DOI: https://doi.org/10.1007/s10470-015-0492-4

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