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A bidirectional neural interface SoC with an integrated spike recorder, microstimulator, and low-power processor for real-time stimulus artifact rejection

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Abstract

This paper presents a neural interface system-on-chip (SoC) featuring combined spike recording, electrical microstimulation, and real-time stimulus artifact rejection (SAR) for bidirectional interfacing with the nervous system. The SoC integrates a spike-recording front-end with input noise voltage of 3.42 μVrms (0.5 Hz–50 kHz), microstimulating back-end for delivering charge-balanced monophasic or asymmetric biphasic current pulses of <100 μA with passive discharge, and μW-level digital signal processing (DSP) unit for real-time SAR based on template subtraction. The DSP unit initializes its embedded 16b, 4 K static random-access memory with the first recorded stimulus artifact to reduce the operation time in generating an accurate artifact template signal for subtraction. Fabricated in AMS 0.35 μm 2P/4M CMOS, the 3.1 × 3.1-mm2 SoC has been characterized in benchtop tests and neurobiological experiments with isolated buccal ganglia of an Aplysia californica (a marine mollusk). The SoC can successfully remove mV-range stimulus artifacts with duration up to ~115 ms from the contaminated neural data in real time and recover µV-range extracellular neural spikes that occur on the tail end of the artifacts. The average root-mean-square (rms) value of the pre-processed stimulus artifact is reduced by a factor of ~24–30 post-processing, with DSP unit power consumption of <25 µW from 1.5 V.

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Acknowledgments

This work was supported by the Department of Defense Traumatic Brain Injury—Investigator-Initiated Research Award Program under Award W81XWH-10-1-0741 (to P. Mohseni) and National Institutes of Health grant NS047073 (to H. J. Chiel). The authors would like to thank J. McManus, Case Western Reserve University, Cleveland, OH, for his assistance in conducting the neurobiological experiments, as well as Dr. D. Guggenmos and Prof. R. Nudo, University of Kansas Medical Center, Kansas City, KS, for providing the prerecorded rat neural dataset. The authors would also like to thank Dr. M. Azin, QualComm, San Diego, CA, and Prof. M. Buchner, Case Western Reserve University, for helpful discussions that made this work possible.

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Authors and Affiliations

  1. Electrical Engineering and Computer Science Department, Case Western Reserve University, Cleveland, OH, 44106, USA

    Kanokwan Limnuson & Pedram Mohseni

  2. Department of Biology, Case Western Reserve University, Cleveland, OH, 44106, USA

    Hui Lu & Hillel J. Chiel

  3. Advanced Platform Technology (APT) Center – A Veterans Affairs (VA) Research Center of Excellence, Cleveland, OH, 44106, USA

    Pedram Mohseni

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  1. Kanokwan Limnuson
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Correspondence to Pedram Mohseni.

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Limnuson, K., Lu, H., Chiel, H.J. et al. A bidirectional neural interface SoC with an integrated spike recorder, microstimulator, and low-power processor for real-time stimulus artifact rejection. Analog Integr Circ Sig Process 82, 457–470 (2015). https://doi.org/10.1007/s10470-015-0489-z

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