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The first reactive synthesis competition (SYNTCOMP 2014)

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Abstract

We introduce the reactive synthesis competition (SYNTCOMP), a long-term effort intended to stimulate and guide advances in the design and application of synthesis procedures for reactive systems. The first iteration of SYNTCOMP is based on the controller synthesis problem for finite-state systems and safety specifications. We provide an overview of this problem and existing approaches to solve it, and report on the design and results of the first SYNTCOMP. This includes the definition of the benchmark format, the collection of benchmarks, the rules of the competition, and the five synthesis tools that participated. We present and analyze the results of the competition and draw conclusions on the state of the art. Finally, we give an outlook on future directions of SYNTCOMP.

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Notes

  1. See also: the Hardware Model Checking Competition, http://fmv.jku.at/hwmcc/. Accessed February 2016.

  2. For simplicity, we assume that is a latch. If is not a latch in the given monitor circuit, then it can be described as a formula \(f(L,X_u,X_c)\). In this case we can obtain a problem in the described form by extending the circuit with a new latch that takes \(f(L,X_u,X_c)\) as an input and provides output .

  3. http://www.eecs.berkeley.edu/~alanmi/abc/. Accessed February 2016.

  4. http://fmv.jku.at/aiger/. Accessed February 2016.

  5. http://fmv.jku.at/hwmcc/. Accessed February 2016.

  6. The reason for disallowing original AND-gates is that we want the controller to work only based on the state of the given circuit (i.e., values of latches), and the uncontrollable inputs. Original AND-gates can be duplicated in the controller if necessary.

  7. Numbers regarding realizability are to the best of our knowledge. The realizability status has not been verified for all benchmark instances.

  8. http://lit2.ulb.ac.be/acaciaplus/. Accessed February 2016.

  9. https://github.com/gaperez64/acacia_ltl2aig. Accessed February 2016.

  10. http://vlsi.colorado.edu/~vis/. Accessed February 2016.

  11. http://www.eecs.berkeley.edu/~alanmi/abc/. Accessed February 2016.

  12. http://fmv.jku.at/aiger/. Accessed February 2016.

  13. http://github.com/ltlmop/slugs. Accessed February 2016.

  14. https://bitbucket.org/art_haali/aisy-classroom. Accessed February 2016.

  15. http://www.iaik.tugraz.at/content/research/opensource/lily/. Accessed February 2016.

  16. We conjecture that this version is more challenging because it is based on a large LTL specification, which is translated to a single, very big Büchi automaton in the first step of the ltl2aig routine. This results in a circuit that is much more complex than the ones from Sect. 4.3.

  17. http://www.react.uni-saarland.de/tools/unbeast/. Accessed February 2016.

  18. In particular, non-trivial parallelization is difficult for BDD-based tools, since none of the existing parallel BDD packages supports all features needed for the optimizations mentioned in Sect. 2.3.

  19. The quality ranking was devised for the second SYNTCOMP and was applied to the results of the first competition only after the presentation of results at SYNT and CAV 2014.

  20. This rule only had to be used in one instance, where a benchmark was solved by only one tool, and was reported to be realizable although unrealizable was the expected outcome. In our analysis it turned out that the tool was correct, and the initial classification as unrealizable was wrong.

  21. http://ecee.colorado.edu/wpmu/iimc/. Accessed February 2016.

  22. http://fmv.jku.at/aiger/. Accessed February 2016.

  23. http://vlsi.colorado.edu/~fabio/CUDD/. Accessed February 2016.

  24. http://www.eecs.berkeley.edu/~alanmi/abc/. Accessed February 2016.

  25. Analysis of results and subsequent inspection of the source code by the tool author showed that due to a bug the parallel version did not work as intended, and instead used two threads with identical strategy. As can be seen in the results section, this lead to a decreased performance overall.

  26. http://termite2.org. Accessed February 2016.

  27. https://hackage.haskell.org/package/attoparsec. Accessed February 2016.

  28. http://www.adaptivecomputing.com/products/open-source/torque/. Accessed February 2016.

  29. As mentioned in Sect. 6.1, AbsSynthe was supposed to compete in different configurations, but due to a miscommunication was always started in the same configuration. The results presented here for the relative ranking differ from those presented at CAV 2014 in that only one of the three identical configurations of AbsSynthe is counted in the sequential tracks.

  30. This benchmark was found to be realizable by the tool, although it was classified as unrealizable by the benchmark authors. Our analysis confirmed it to be realizable.

  31. Due to a bug, the parallel version of Realizer performed worse than the sequential version, as mentioned in Sect. 6.

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Acknowledgments

We thank the anonymous reviewers for their detailed and insightful comments on drafts of this article. We thank Armin Biere for his advice on running a competition, and Ayrat Khalimov for supplying the reference implementation Aisy for the competition. The organization of SYNTCOMP 2014 was supported by the Austrian Science Fund (FWF) through projects RiSE (S11406-N23) and QUAINT (I774-N23), by the German Research Foundation (DFG) as part of the Transregional Collaborative Research Center “Automatic Verification and Analysis of Complex Systems” (SFB/TR 14 AVACS) and through project “Automatic Synthesis of Distributed and Parameterized Systems” (JA 2357/2-1), as well as by the Institutional Strategy of the University of Bremen, funded by the German Excellence Initiative. The development of AbsSynthe was supported by an F.R.S.-FNRS fellowship, and the ERC inVEST (279499) project. The development of Basil was supported by the Institutional Strategy of the University of Bremen, funded by the German Excellence Initiative. The development of \(\texttt {Demiurge}\) was supported by the FWF through projects RiSE (S11406-N23, S11408-N23) and QUAINT (I774-N23). The development of Realizer was supported by the DFG as part of SFB/TR 14 AVACS. The development of Simple BDD Solver was supported by a gift from the Intel Corporation, and NICTA is funded by the Australian Government through the Department of Communications and the Australian Research Council through the ICT Centre of Excellence Program.

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Authors and Affiliations

  1. Graz University of Technology, Graz, Austria

    Swen Jacobs, Roderick Bloem, Timotheus Hell & Robert Könighofer

  2. Saarland University, Saarbrücken, Germany

    Swen Jacobs & Leander Tentrup

  3. Université Libre de Bruxelles, Brussels, Belgium

    Romain Brenguier, Guillermo A. Pérez, Jean-François Raskin & Ocan Sankur

  4. University of Bremen, Bremen, Germany

    Rüdiger Ehlers

  5. DFKI GmbH, Bremen, Germany

    Rüdiger Ehlers

  6. NICTA, Sydney, Australia

    Leonid Ryzhyk & Adam Walker

  7. Carnegie Mellon University, Pittsburgh, USA

    Leonid Ryzhyk

  8. CNRS, IRISA, Rennes, France

    Ocan Sankur

  9. Johannes-Kepler-University Linz, Linz, Austria

    Martina Seidl

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  1. Swen Jacobs
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Jacobs, S., Bloem, R., Brenguier, R. et al. The first reactive synthesis competition (SYNTCOMP 2014). Int J Softw Tools Technol Transfer 19, 367–390 (2017). https://doi.org/10.1007/s10009-016-0416-3

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