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Fabrication and characterization of n-Si/SiON/metal gate structure for future MOS technology

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Abstract

We present the fabrication and characterization of n-Si/SiON/metal (metal–oxide–semiconductor (MOS)) gate structure with silicon oxynitride (SiON) as insulating layer and different metal films such as Aluminium (Al), Titanium nitride (TiN) and Platinum (Pt) as gate electrode. Cheung’s method has been used to calculate the barrier height (ϕbo) and ideality factor (η) of these three different diodes varying in different metal electrode types. The interface state density (Dit), dielectric constant (k), effective oxide charge (Qeff) and work function (Φm) have also been extracted from the capacitance–voltage (C–V) experimental data. A gradual improvement in various parameters for n-Si/SiON/metal gate stack has been observed after annealing the SiON film under controlled conditions e.g., TiN metal gate electrode shows good electrical characteristics with improved ideality factor (1.7) and barrier height (0.69 eV) over the Al and Pt/Ti gate electrodes due to the modified interface chemistry. The extracted Φm for TiN gate electrode is ~ 5.13 eV which is in good agreement with the previous results reported in literature. The value of Dit reduces, whereas the value of k increases upon post deposition annealing (PDA) for all the metal gate electrodes. An increase in Dit causes an increase in the η for Al and Pt/Ti metal gates as compared to TiN metal gate. The influences of PDA process on the electrical characteristics of n-Si/SiON/metal MOS diodes have also been investigated for as-deposited and annealed MOS diode.

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Acknowledgements

Authors extend their sincere thanks to CEN IITB for providing us fabrication and characterization facilities and also for financial assistance under INUP scheme, which have been sponsored by DIT, MCIT, Government of India and the author (Rakesh Vaid) thank the University Grants Commission (UGC) for providing financial assistance under major research project (MRP-MAJOR-ELEC-2013-22797) under the 12th plan period.

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Authors and Affiliations

  1. Department of Electronics, University of Jammu, Jammu, 180006, India

    Renu Rajput, Richa Gupta & Rakesh Vaid

  2. School of Electrical and Electronic Engineering, University of Manchester, Manchester, UK

    Rakesh K. Gupta

  3. Department of Mechanical System Science, Graduate School of Science and Engineering, Yamagata University, Jonan, 4-3-16, Yonezawa, Yamagata, 992-8510, Japan

    Ajit Khosla

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  1. Renu Rajput
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  2. Richa Gupta
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Correspondence to Rakesh Vaid.

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Rajput, R., Gupta, R., Gupta, R.K. et al. Fabrication and characterization of n-Si/SiON/metal gate structure for future MOS technology. Microsyst Technol 24, 4179–4185 (2018). https://doi.org/10.1007/s00542-017-3703-3

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  • DOI: https://doi.org/10.1007/s00542-017-3703-3

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