Skip to main content
SpringerLink
Log in

Alternate lanthanum oxide/silicon oxynitride-based gate stack performance enhancement due to ultrathin oxynitride interfacial layer for CMOS applications

  • Published:
Journal of Materials Science: Materials in Electronics Aims and scope Submit manuscript

Abstract

Metal–insulator–semiconductor (MIS)-based Pt/La2O3/SiOXNY/p-Si/Pt structures are fabricated using ultrathin silicon oxynitride (SiOXNY ~ 4 nm) interfacial layer underneath of lanthanum (III) oxide (La2O3 ~ 7.8 nm) with Pt as gate electrode for CMOS applications. Capacitance–voltage (C–V) characteristics of Pt/La2O3/SiOXNY/p-Si/Pt at 500 kHz showed a positive gate bias threshold voltage (Vth) shift of ~ 0.43 V (~ 43.8%) and flat-band (Vfb) shift of ~ 1.24 V (~ 42.3%) as compared to Pt/La2O3/p-Si/Pt MIS structures, attributing to the reduction in effective positive oxide charges at La2O3/SiOXNY/Si gate stack. Likewise, conductance–voltage (G–V) characteristics show ~ 0.56 (~ 44.4%) reduction in FWHM for Pt/La2O3/SiOXNY/p-Si/Pt as compared to Pt/La2O3/p-Si/Pt MIS structures revealing the reduction in interface states at La2O3/SiOXNY/Si interface. There is a considerable reduction of effective oxide charge concentration (Neff) ~ 3.99 × 1010 cm−2 by (~ 15.2%) and ~ 56.8% lower gate leakage current density ~ 4.47 × 10−7 A/cm2 (|J|–V) at − 1 V for SiOXNY based MIS structures w.r.t its counterpart. Capacitance–time (C–t) characteristics, constant voltage stress (CVS) and temperature measurements for C–V and |J|–V demonstrate the considerable retention ~ 12 years, electrical improvement and reliability of MIS structures. The depth profile analysis X-ray photoelectron spectroscopy (XPS) for SiOXNY/Si gate stack clearly reveals that less nitrogen concentration in bulk than SiOXNY/Si interface. Atomic force microscopy (AFM) micrographs of La2O3/Si and SiOXNY/Si showed the significantly lesser r.m.s roughness of ~ 1.11 ± 0.39 nm and ~ 0.97 ± 0.11 nm, respectively. Thus, the ultrathin SiOXNY interfacial layer underneath of La2O3 demonstrates a significantly improved electrical performance and prelude the gate stack strong potential for reliable CMOS logic devices and integrated circuits.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7

Similar content being viewed by others

References

  1. A.I. Kingon, J.P. Maria, S.K. Streiffer, Nature 406, 1032 (2000)

    CAS  Google Scholar 

  2. J.M.A.G.D. Wilk, R.M. Wallace, Appl. Phys. Rev. 89, (2001)

  3. J. Robertson, Eur. Phys. J. Appl. Phys. 28, 265 (2004)

    CAS  Google Scholar 

  4. R. Khosla, S.K. Sharma, J. Vac. Sci. Technol. B 36, 012201 (2018)

    Google Scholar 

  5. J. Robertson, R.M. Wallace, Mater. Sci. Eng. R 88, 1 (2015)

    Google Scholar 

  6. B.H. Lee, S.C. Song, R. Choi, P. Kirsch, IEEE Trans. Electron. Devices 55, 8 (2008)

    CAS  Google Scholar 

  7. J. Robertson, Rep. Prog. Phys. 69, 327 (2006)

    CAS  Google Scholar 

  8. H. Iwai, S. Ohmi, S. Akama, C. Ohshima, A. Kikuchi, I. Kashiwagi, J. Taguchi, H. Yamamoto, J. Tonotani, Y. Kim, I. Ueda, A. Kuriyama, Y. Yoshihara, IEEE Int. Electron. Devices Meet. (2002), pp. 625–628

  9. K. Yim, Y. Yong, J. Lee, K. Lee, H. Nahm, J. Yoo, C. Lee, C.S. Hwang, S. Han, Nat. NPG Asia Mater. 7, 1 (2015)

    Google Scholar 

  10. R. Khosla, P. Kumar, S.K. Sharma, IEEE Trans. Device Mater. Reliab. 15, 610 (2015)

    CAS  Google Scholar 

  11. F.-C. Chiu, H.-W. Chou, J.Y.-M. Lee, J. Appl. Phys. 97, 103503 (2005)

    Google Scholar 

  12. J. Robertson, J. Appl. Phys. 104, 124111 (2008)

    Google Scholar 

  13. S. Abermann, C. Henkel, O. Bethge, E. Bertagnolli, Proc. 10th Int. Conf. Ultim. Integr. Silicon, ULIS (2009)

  14. E.P. Gusev, V. Narayanan, M.M. Frank, IBM J. Res. Dev. 50, 387 (2006)

    CAS  Google Scholar 

  15. B. Sen, B.L. Yang, H. Wong, C.W. Kok, M.K. Bera, P.K. Chu, A. Huang, K. Kakushima, H. Iwai, IEEE Conference on Electron Devices and Solid-State Circuits (IEEE, Tainan, 2007)

    Google Scholar 

  16. W. Kim, W.J. Maeng, K. Moon, J. Myoung, H. Kim, Thin Solid Films 519, 362 (2010)

    CAS  Google Scholar 

  17. X. Wang, H. Liu, C. Fei, L. Zhao, S. Chen, S. Wang, AIP Adv. 6, 065224 (2016)

    Google Scholar 

  18. R. Khosla, E.G. Rolseth, P. Kumar, S.S. Vadakupudhupalayam, S.K. Sharma, J. Schulze, IEEE Trans. Device Mater. Reliab. 17, 80 (2017)

    CAS  Google Scholar 

  19. T. Perng, C. Chien, C. Chen, M. Yang, P. Lehnen, C. Chang, T. Huang, IEEE Trans. Electron. Devices 25, 784 (2004)

    CAS  Google Scholar 

  20. T. Wang, C. Chang, J. Hwu, IEEE Sens. J 6, 1468 (2006)

    CAS  Google Scholar 

  21. H. Uribe-vargas, J. Molina-reyes, E. Ortega, A. Ponce, IEEE Electron. Device Lett. 39, 1461 (2018)

    CAS  Google Scholar 

  22. Y. Zhao, K. Kita, K. Kyuno, A. Toriumi, Appl. Phys. Lett. 94, 042901 (2009)

    Google Scholar 

  23. H. Jin, S.K. Oh, H.J. Kang, Surf. Interface Anal. 38, 1564 (2006)

    CAS  Google Scholar 

  24. D.A. Buchanan, IBM J. Res. Dev. 43, 245 (1999)

    CAS  Google Scholar 

  25. J.R. Pfiester, F.K. Baker, T.C. Mele, H.-H. Tseng, P.J. Tobin, J.D. Hayden, J.W. Miller, C.D. Gunderson, L.C. Parrillo, IEEE Trans. Electron. Devices 37, 842 (1990)

    Google Scholar 

  26. D. Mathiot, A. Straboni, E. Andre, P. Debenest, J. Appl. Phys. 73, 8215 (1993)

    CAS  Google Scholar 

  27. E.P. Gusev, H.-C. Lu, E.L. Garfunkel, T. Gustafsson, M.L. Green, IBM J. Res. Dev. 43, 265 (1999)

    CAS  Google Scholar 

  28. T. Ando, Materials (Basel). 478 (2012)

  29. B. Balland, A. Glachant, Instabilities in Silicon Devices (Elsevier, Amsterdam, 1999)

    Google Scholar 

  30. C.V. Ramana, R.S. Vemuri, V.V. Kaichev, V.A. Kochubey, A.A. Saraev, V.V. Atuchin, ACS Appl. Mater. Interfaces 3, 4370 (2011)

    CAS  Google Scholar 

  31. R. Leitsmann, F. Lazarevic, M. Drescher, E. Erben, J. Appl. Phys. 121, 234501 (2017)

    Google Scholar 

  32. Nicollian and Brews, MOS Physics and Technology (Wiley Interscience, New York, 2003)

    Google Scholar 

  33. M.L. Green, E.P. Gusev, R. Degraeve, E.L. Garfunkel, J. Appl. Phys. 90, 2057 (2001)

    CAS  Google Scholar 

  34. K. Kakushima, K. Tachi, M. Adachi, K. Okamoto, S. Sato, J. Song, T. Kawanago, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, Solid State Electron. 54, 715 (2010)

    CAS  Google Scholar 

  35. K. Kakushima, T. Seki, H. Wakabayashi, K. Tsutsui, H. Iwai, Vacuum 140, 14 (2017)

    CAS  Google Scholar 

  36. R. Perera, A. Ikeda, R. Hattori, Y. Kuroki, Thin Solid Films 423, 212 (2003)

    CAS  Google Scholar 

  37. M. Soni, A. Soni, S.K. Sharma, Org. Electron. 51, 48 (2017)

    CAS  Google Scholar 

  38. F.M. Fowkes, D.W. Hess, Appl. Phys. Lett. 377, 1 (1973)

    Google Scholar 

  39. D.K. Schroder, Semiconductor Material and Device Characterization (Wiley, New York, 2006)

    Google Scholar 

  40. R. Khosla, D.K. Sharma, K. Mondal, S.K. Sharma, Appl. Phys. Lett. 105, 152907 (2014)

    Google Scholar 

  41. P.K. Bhatnagar, S.R. Dhariwal, G.P. Srivastava, Phys. Status Solidi 67, 305 (1981)

    CAS  Google Scholar 

  42. R. Clerc, P.O. Sullivan, K.G. Mccarthy, G. Ghibaudo, G. Pananakakis, A. Mathewson, Solid State Electron. 45, 1705 (2001)

    CAS  Google Scholar 

  43. M. Shukla, G. Dutta, R. Mannam, N. Dasgupta, Thin Solid Films 607, 1 (2016)

    CAS  Google Scholar 

  44. M.B. Haider, Nanoscale Res. Lett. 12, 1 (2017)

    CAS  Google Scholar 

  45. Z. Zhuo, Y. Sannomiya, Y. Kanetani, T. Yamada, H. Ohmi, H. Kakiuchi, K. Yasutake, Nanoscale Res. Lett. 201, 1 (2013)

    Google Scholar 

  46. M. Delfino, S. Salimian, D. Hodul, A. Ellingboe, W. Tsai, J. Appl. Phys. 71, 1001 (1992)

    CAS  Google Scholar 

  47. M.S. Donley, D.R. Baer, T.G. Stoebe, Surf. Interface Anal. 11, 335 (1988)

    CAS  Google Scholar 

  48. S. Alexandrova, E. Halova, S. Bakalova, A. Szekeres, A. Marin, P. Osiceanu, M. Gartner, N. Koujuharova, J. Phys. 514, 012035 (2014)

    Google Scholar 

Download references

Acknowledgements

The authors would like to strongly acknowledge Centre for Design and Fabrication of Electronic Devices (C4DFED), and Advanced Materials Research Centre (AMRC), Indian Institute of Technology (IIT) Mandi, India, for the use of various state-of-the-art device fabrication and characterization facilities for present work. Author Prachi Gupta would like to thank ‘INSPIRE Ph.D. Fellowship Programme (research fellowship) support from Department of  Science and Technology (DST) Govt. of India.

Author information

Authors and Affiliations

  1. School of Computing and Electrical Engineering (SCEE), Indian Institute of Technology (IIT) Mandi, Mandi, Himachal Pradesh, 175005, India

    Prachi Gupta, Mahesh Soni & Satinder K. Sharma

Authors
  1. Prachi Gupta
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Mahesh Soni
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Satinder K. Sharma
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Satinder K. Sharma.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Gupta, P., Soni, M. & Sharma, S.K. Alternate lanthanum oxide/silicon oxynitride-based gate stack performance enhancement due to ultrathin oxynitride interfacial layer for CMOS applications. J Mater Sci: Mater Electron 31, 1986–1995 (2020). https://doi.org/10.1007/s10854-019-02718-7

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10854-019-02718-7

Search

Navigation