Abstract
Internet-of-Things applications operate with restricted energy from a battery, and thus, require static random-access memory (SRAM) cells, as the building block of a chip, with less energy consumption to lengthen battery life for long-term operation. In this regard, this paper evaluates the performance of a novel low-energy single-bitline 11-transistor (SB11T) near-threshold SRAM cell while comparing it with the conventional 6 T, Schmitt-trigger 9 T (ST9T), stability- and power-improved 11 T (SPI11T), and single-ended 11 T (SE11T) based on 10-nm common-gate fin-shaped field-effect transistor (FinFET) technology at a near-threshold voltage of 0.45 V. The proposed SB11T cell shows at least 1.04 × higher hold/read stability in terms of hold/read static noise margin, and 1.40 × higher writability in terms of write static noise margin compared to the conventional 6 T cell. It offers 33.08%/13.39% lower read/write delay than the SPI11T cell. Furthermore, a reduction of at least 34.14%/26.04%/56.30% in leakage power/read energy/write energy is achieved by the proposed SB11T cell, at the cost of 1.84 × larger area compared to the conventional 6 T cell. Generally, the proposed design is the best cell from the figure of merit point of view.
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The data that support the finding of this study are available from the corresponding author upon reasonable request.
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Abbasian, E., Grailoo, B. & Nayeri, M. Design of a 10-nm FinFET 11 T Near-Threshold SRAM Cell for Low-Energy Internet-of-Things Applications. Circuits Syst Signal Process 42, 3138–3151 (2023). https://doi.org/10.1007/s00034-022-02251-9
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DOI: https://doi.org/10.1007/s00034-022-02251-9