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A Single-Bitline 9T SRAM for Low-Power Near-Threshold Operation in FinFET Technology

  • Research Article-Electrical Engineering
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Abstract

Static random-access memories (SRAMs), which are the most ubiquitous in modern system-on-chips, suffer from high power dissipation and poor stability in advanced complementary metal–oxide–semiconductor (CMOS) technology due to continuous learning, which leads to increased short-channel effects (SCEs), thereby, leading to use of new nano-devices. The fin-shaped field-effect transistor (FinFET) with lots of impressive attributes like mitigated SCEs is an efficient replacement for CMOS to overcome the aforementioned concerns. In this regard, this paper aims to explore a novel single-bitline 9-transistor (SB9T) SRAM with bit-interleaving capability appropriate for low-power near-threshold operation in 7-nm FinFET technology. The relative performance of the proposed SB9T is estimated by comparing it with other seven contemporary SRAMs such as conventional 6 T, write–read enhanced 8T (WRE8T), transmission gate read decoupled 9T (TGRD9T), one-sided Schmitt-trigger 9T (ST9T), data-independent read port 10T (DIRP10T), PMOS-PMOS-NMOS-based cell core 10T (PPN10T), and feedback-cutting 11 T (FC11T) at a near-threshold supply voltage of 0.5 V. Simulation results inferred that the SB9T offers 1.77 × /1.36 × and 2.35 × /13.13 × /1.30 × improvement in read stability and writability compared to WRE8T/ST9T and 6 T/DIRP10T/PPN10T, respectively. Furthermore, it consumes the best dynamic read power, which is at least 1.50 × , the third-best dynamic write power, and the second-best static power. The proposed SB9T SRAM offers 2.89 × /2.37 × improvement in dynamic write power/static power, at the expense of 1.742 × area overhead, compared to 6 T.

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Data availability

The data that support the finding of this study are available from the corresponding author upon reasonable request.

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Acknowledgements

Authors acknowledge the funding support of the Babol Noshirvani University of Technology through grant program No. BNUT/389023/1400. Also, they acknowledge the support and lab facility provided by the Department of ECE, Manipal University Jaipur, Jaipur, India.

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Authors and Affiliations

  1. Faculty of Electrical and Computer Engineering, Babol Noshirvani University of Technology, Babol, Iran

    Erfan Abbasian & Morteza Gholipour

  2. Department of Electronics & Communication Engineering, Manipal University Jaipur, Jaipur, India

    Shilpi Birla

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  1. Erfan Abbasian
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  2. Morteza Gholipour
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  3. Shilpi Birla
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Correspondence to Erfan Abbasian.

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Abbasian, E., Gholipour, M. & Birla, S. A Single-Bitline 9T SRAM for Low-Power Near-Threshold Operation in FinFET Technology. Arab J Sci Eng 47, 14543–14559 (2022). https://doi.org/10.1007/s13369-022-06821-6

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  • DOI: https://doi.org/10.1007/s13369-022-06821-6

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