Abstract
This paper investigates the effect of temperature on the wireless performance characteristics, i.e., linearity and harmonic distortion for the vertically stacked junctionless field effect transistor (JL-NSFET) at gate length (lg) = 16 nm. The transfer characteristics curve (Id-Vg), transconductance (gm), and its second- and third-order derivatives, i.e., gm2 and gm3 performances are explored. The detailed analysis reveals that the temperature shows a profound influence on VIP3 and IIP3 giving the best linearity for the temperature range 77–200 ̊K with better gate drive. However, the second- and third-order derivatives of distortion, i.e., HD2 and HD3 are not much affected by temperature giving least distortions with negligible change. Therefore, the simulated JL-NSFET optimizes the device linearity and harmonic distortion performances with best suitable for RF and wireless applications.
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References
Emona D, Avik C, Abhijit M (2020) Relative study of analog performance, linearity, and harmonic distortion between junctionless and conventional SOI FinFETs at elevated temperatures. J Electron Mater 49(5):3309–3316
Barman KR, Baishya S (2020) Study of temperature effect on analog/RF and linearity performance of dual material gate (DMG) vertical super-thin body (VSTB) FET. Silicon, pp 1–10
Tayal S, Bhattacharya S, Jena B, Ajayan J, Muchahary D, Singla P (2021) Linearity performance and harmonic distortion analysis of IGE junctionless silicon nanotube-FET for wireless applications. Silicon, pp 1–6
Tayal S, Mittal V, Jadav S, Gupta S, Nandi A, Krishan B (2020) Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: an Analog/RF prospective. Cryogenics 108:103087
Awadhiya B, Pandey S, Nigam K, Kondekar PN (2017) Effect of ITC’s on linearity and distortion performance of junctionless tunnel field effect transistor. Superlattices Microstruct 111:293–301
Gupta N, Chaujar R (2016) Investigation of temperature variations on analog/RF and linearity performance of stacked gate GEWE-SiNW MOSFET for improved device reliability. Microelectron Reliab 64:235–241
Valasa S, Tayal S, Thoutam LR (2022) Optimization of design space for vertically stacked junctionless nanosheet FET for analog/RF applications. Silicon, pp 1–10
Madan J, Chaujar R (2016) Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability. IEEE Trans Device Mater Reliab 16(2):227–234
Valasa S, Shinde JR, Ramji DR, Avunoori S (2021) A power and delay efficient circuit for CMOS phase detector and phase frequency detector. In: 2021 6th international conference on communication and electronics systems (ICCES), pp 77–82. IEEE
Kumar SP, Agrawal A, Chaujar R, Gupta RS, Gupta M (2011) Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor. Microelectron Reliab 51(3):587–596
Kumar A (2017) Effect of trench depth and gate length shrinking assessment on the analog and linearity performance of TGRC-MOSFET. Superlattices Microstruct 109:626–640
Kumar A, Gupta N, Tripathi SK, Tripathi MM, Chaujar R (2020) Performance evaluation of linearity and intermodulation distortion of nanoscale GaN-SOI FinFET for RFIC design. AEU-Int J Electron Commun 115:153052
Rewari S, Goel A, Verma S, Gupta RS (2019) Linearity and intermodulation distortion assessment of underlap engineered cylindrical junctionless surrounding gate MOSFET for low noise CMOS RFIC design. In: 2019 IEEE 16th India council international conference (INDICON), pp 1–4. IEEE
Tayal S, Nandi A (2018) Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance. Cryogenics 92:71–75
Saha R, Bhowmick B, Baishya S (2018) Temperature effect on RF/analog and linearity parameters in DMG FinFET. Appl Phys A 124(9):1–10
Lee SY, Lee YS, Jeong YH (2006) A novel phase measurement technique for IM3 components in RF power amplifiers. IEEE Trans Microw Theory Tech 54(1):451–457
Yu C, Yuan JS, Yang H (2004) MOSFET linearity performance degradation subject to drain and gate voltage stress. IEEE Trans Device Mater Reliab 4(4):681–689
Yum TY, Chiu L, Chan CH, Xue Q (2006) High-efficiency linear RF Amplifier-a unified circuit approach to achieving compactness and low distortion. IEEE Trans Microw Theory Tech 54(8):3255–3266
Kumar B, Chaujar R (2021) TCAD temperature analysis of gate stack gate all around (GS-GAA) FinFET for improved RF and wireless performance. Silicon, pp 1–13
Ajayan J, Nirmal D, Tayal S, Bhattacharya S, Arivazhagan L, Fletcher AA, Murugapandiyan P, Ajitha D (2021) Nanosheet field effect transistors-A next generation device to keep Moore’s law alive: an intensive study. Microelectron J 105141
Ajayan J, Nirmal D (2015) A review of InP/InAlAs/InGaAs based transistors for high frequency applications. Superlattices Microstruct 86:1–19
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Valasa, S., Tayal, S., Thoutam, L.R. (2023). Performance Analysis of Temperature on Wireless Performance for Vertically Stacked Junctionless Nanosheet Field Effect Transistor. In: Giri, C., Iizuka, T., Rahaman, H., Bhattacharya, B.B. (eds) Emerging Electronic Devices, Circuits and Systems. Lecture Notes in Electrical Engineering, vol 1004. Springer, Singapore. https://doi.org/10.1007/978-981-99-0055-8_2
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DOI: https://doi.org/10.1007/978-981-99-0055-8_2
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