Abstract
Silicon validation is the most time-consuming process in the VLSI design flow. It mainly involves pre-silicon validation and post silicon validation. Post-silicon validation has limited visibility and control of internal signals and is the most time-consuming task. To help in narrowing down the features responsible for failure and reproduce the bug, the power of machine learning is leveraged. Based on the data provided, machine learning is used to provide the feature weights that control the failure of the device, thereby leading to faster reproduction of the failure. The framework that stresses the CPU requires manual intervention for providing test vectors and hence to have a faster response, the framework is automated with a reset mechanism so that it can include tests that are expected to fail on the device. Based on sample data, the machine learning model using supervised learning algorithms is developed. Results show that the model is accurately able to predict the features responsible for failure when applied on real time chip data. Due to automation, there is about 66% saving in time when compared to the manual process, thereby giving more time for more experiments to be run on the device and faster time to market.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Pridhiviraj P, Tomar Dheerendra S, Muralidhar P (2015) Adaptive post-silicon server validation using machine learning. Int J Appl Inf Syst 9(1):24–32
DeOrio A, Li Q, Burgess M, Bertacco V (2013) Machine learning-based anomaly detection for post-silicon bug diagnosis. In: Design, Automation & Test in Europe Conference & Exhibition (DATE)
Zhuo C, Yu B, Gao D (2017) Accelerating chip design with machine learning: from pre-silicon to post-silicon. In: 30th IEEE International System-on-Chip Conference (SOCC)
Mandouh EE, Wassal AG (2017) Application of machine learning techniques in post-silicon debugging and bug localization. J Electron Test 34(2):163–181
Park S, Bracy A, Wang H, Mitra S (2010) Blog: post-silicon bug localization in processors using bug localization graphs. In: Proceedings of the DAC
Mitra S, Seshia SA, Nicolici N (2010) Post-silicon validation opportunities, challenges and recent advances. In: Proceedings of the DAC
Wang S, Wei W (2009) Machine learning-based volume diagnosis. In: Proceedings of the DATE
Kim D, Kang P, Cho S, Lee H, Doh S (2012) Machine learning-based novelty detection for faulty wafer detection in semiconductor manufacturing. Exp Syst Appl 39(4):4075–4083
He QP, Wang J (2007) Fault detection using the k-nearest neighbor rule for semiconductor manufacturing processes. IEEE Trans Semicond Manuf 20(4):345–354
DeOrio A, Khudia DS, Bertacco V (2011) Post-silicon bug diagnosis with inconsistent executions. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Basu K, Mishra P (2013) Rats restoration-aware trace signal selection for post- silicon validation. IEEE Trans Very Large-Scale Integr (VLSI) Syst 13(4):605–613
Keshava J, Hakim N, Prudvi C (2010) Post-silicon validation challenges: how EDA and academia can help. In: Design Automation Conference
Josephson D (2006) The good, the bad, and the ugly of silicon debug. In: 43rd ACM/IEEE Design Automation Conference
Bishop CM (2007) Pattern Recognition and Machine Learning
Mitchell T (1997) Machine Learning
Rahmani K, Mishra P (2017) Feature-based signal selection for post-silicon debug using machine learning. IEEE Trans Emerg Top Comput 8:907–915
Rahmani K, Ray S, Mishra P (2017) Postsilicon trace signal selection using machine learning techniques. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(2):570–580
Youn S, Gu C, Kim J (2014) Probabilistic bug localization via statistical inference based on partially observed data. In: Proceedings of the DAC, pp 1–6
Yang H, Su J, Zou Y, Yu B, Young EFY (2017) Imbalance aware lithography hotspot detection: a deep learning approach. In: Proceedings of the DAC, pp 62:1–62:6
Capodieci L (2017) Data analytics and machine learning for design-process-yield optimization in electronic design automation and IC semiconductor manufacturing. In: Proceedings of the CSTIC, pp 1–3
De Paula FM, Gort M, Hu AJ, Wilton SJE, Yang J (2008) Backspace: formal analysis for post-silicon debug. In: Formal Methods in Computer-Aided Design
Wagner I, Bertacco V (2008) Reversi: post-silicon validation system for modern microprocessors. In: IEEE International Conference on Computer Design
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2021 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Ashish, B.P., Palecha, N. (2021). Adaptive Feedback Mechanism for Silicon Bug Detection. In: Nath, V., Mandal, J.K. (eds) Proceeding of Fifth International Conference on Microelectronics, Computing and Communication Systems. Lecture Notes in Electrical Engineering, vol 748. Springer, Singapore. https://doi.org/10.1007/978-981-16-0275-7_46
Download citation
DOI: https://doi.org/10.1007/978-981-16-0275-7_46
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-16-0274-0
Online ISBN: 978-981-16-0275-7
eBook Packages: EngineeringEngineering (R0)