Post-Silicon Signal Selection Using Machine Learning

Abstract

A key constraint in post-silicon validation and debug is limited observability of internal signals. Knowledge of only primary outputs can lead to an observability of a few internal signals. The most widely used on-chip testing infrastructure is scan chains, which can provide reasonable observability. However, using scan chain involves loading of input vectors in test mode, and therefore, is not suitable for signal tracing during normal execution. Instead, a small trace buffer is commonly used to meet this purpose. Size of trace buffer is limited (can only trace a small number of signals) due to area and energy constraints. The goal of signal selection is to maximize observability by selecting the correct set of signals (hundreds out of billions) for trace buffer. Many signal selection techniques have been proposed over the years. Metric- based techniques do static analysis on design to select profitable signals. They often use greedy algorithms, which are fast but lead to poor restoration quality. In contrast, simulation-based selection techniques provide superior restorability but incur significant runtime overhead. A hybrid between these two approaches has also been proposed, which trades-off some restoration performance to reduce runtime. Recently, machine learning based signal selection techniques are emerging as the most promising one. This chapter describes two machine learning based signal selection methods. The first method trains a model to predict restoration quality based on the selected signals. This method improves runtime by performing only a small number of simulations for training. The second method demonstrates how runtime can be further improved by running simulation on small-scale designs with the similar characteristic as the actual one.