Abstract
Approximate computing is an emerging paradigm to create energy-efficient computing systems. Most of the image processing applications are inherently error-resilient and can tolerate the error up to a certain limit. In such applications, energy can be saved by pruning the data path modules such as a multiplier. In this paper, we propose a new truncation scheme and an error correction term which are applied to recursive multiplier architecture. Further, truncation method and correction term that compensates the error in the proposed approximate multiplier significantly reduce the area, delay and power. Finally, the proposed multiplier is validated on an image sharpening algorithm. Simulations carried out clearly prove that the proposed multiplier performs better compared to the existing multipliers.
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References
Biswas K, Wu H, Ahmadi M (2006) Fixed-width multi-level recursive multipliers. In: 2006 Fortieth Asilomar conference on signals, systems and computers. IEEE
Townsend WJ, Swartzlander E Jr, Abraham JA (2003) A comparison of Dadda and Wallace multiplier delays. In: Advanced signal processing algorithms, architectures, and implementations XIII, vol 5205. International Society for Optics and Photonics
Kulkarni P, Gupta P, Ercegovac M (2011) Trading accuracy for power with an underdesigned multiplier architecture. In: 2011 24th International conference on VLSI design. IEEE, pp 346–351
Mahdiani HR, Ahmadi A, Fakhraie SM, Lucas C (2009) Bioinspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications. IEEE Trans Circ Syst I Regul Pap 57(4):850–862
Bhardwaj K, Mane PS, Henkel J (2014) Power-and area-efficient approximate Wallace tree multiplier for error-resilient systems. In: Fifteenth international symposium on quality electronic design. IEEE, pp 263–269
Yang Z, Han J, Lombardi F (2015) Approximate compressors for error-resilient multiplier design. In: 2015 IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFTS). IEEE, pp 183–186
Ha M, Lee S (2017) Multipliers with approximate 4–2 compressors and error recovery modules. IEEE Embed Syst Lett 10(1):6–9
Danysh AN, Swartzlander EE (1998) A recursive fast multiplier. In: Conference record of thirty-second Asilomar conference on signals, systems and computers (Cat. No. 98CH36284), vol 1. IEEE
Karatsuba A, Ofman Y (1963) Multiplication of multidigit numbers on automata. Sov Phys Dokl 7
Wallace CS (1964) A suggestion for a fast multiplier. IEEE Trans Electron Comput 1:14–17
Parhami B (2010) Computer arithmetic, vol 20. Oxford University Press, Oxford
Lau MSK, Ling K-V, Chu Y-C (2009) Energy-aware probabilistic multiplier: design and analysis. In: Proceedings of the 2009 international conference on compilers, architecture, and synthesis for embedded systems. ACM
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Sai Revanth Reddy, C., Anil Kumar, U., Ahmed, S.E. (2020). Design of Efficient Approximate Multiplier for Image Processing Applications. In: Goel, N., Hasan, S., Kalaichelvi, V. (eds) Modelling, Simulation and Intelligent Computing. MoSICom 2020. Lecture Notes in Electrical Engineering, vol 659. Springer, Singapore. https://doi.org/10.1007/978-981-15-4775-1_55
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DOI: https://doi.org/10.1007/978-981-15-4775-1_55
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