Abstract
SoC FPGA are shrinking is size with advancement in the technologies. Miniaturization alone may not be sufficient to meet user requirements and hence security challenges remain unsolved. Existing approaches have their own limitations in terms of area and power. A model for two factor authentication is proposed with low- power, area and highly automative. It consists of a hybrid Physical unclonable functions (PUFs), which is used to abstract the unique ID of a chip and finite state machine (FSM) to verify that the Intellectual property (IP) is authentic or not. Recent hardware security applications such as IP protection, IC metering, hardware signature and obfuscation are mostly using PUF. Though most of these applications require a database to store the random outputs and complex security algorithms. This in turn increases the area, power, cost and energy consumption. A lightweight hybrid PUF model consisting of arbitrary and butterfly PUF along with the two-level FSM is projected for such security breaches which can be used for many IOT applications. Experimental results show that the area and power consumed is 5% and 9% respectively, for authenticating 26 IP in 13.25 s which is less than that of the conventional design.
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Kokila, J., Baby Chellam, M., Murali Das, A., Ramasubramanian, N. (2018). Light Weight Two-Factor Authentication Using Hybrid PUF and FSM for SOC FPGA. In: Bhattacharyya, P., Sastry, H., Marriboyina, V., Sharma, R. (eds) Smart and Innovative Trends in Next Generation Computing Technologies. NGCT 2017. Communications in Computer and Information Science, vol 828. Springer, Singapore. https://doi.org/10.1007/978-981-10-8660-1_29
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