Abstract
This paper presents a design of 4-channel Time-to-Digital Convertor (TDC) ASIC based on vernier ring oscillator technique. This technique implements two ring oscillators with very slight difference in time periods, which defines the resolution of TDC. The slight difference in time period is generated by using different fan-out load of the delay cell used to make respective ring oscillators. An on-chip calibration circuit provides the oscillator time period accurately for corrections, thereby reducing PVT (process, voltage, and temperature) variations. The TDC has been implemented using standard cell library of 0.35 μm commercial CMOS technology, achieving a resolution of 114 ps with a dynamic range of 1.8 μs and power consumption of 23 mW/channel.
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Acknowledgments
Authors would like to thank Shri Sekhar Basu, Director BARC; Dr. T.S. Ananthakrishnan, Head, Electronics Division, BARC; Dr. V. M. Datar, Head, Nuclear Physics Division, BARC and Prof. N.K. Mondal of TIFR for their support and encouragement.
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Hari Prasad, K., Sukhwani, M., Saxena, P., Pithawa, C.K., Chandratre, V.B. (2013). A CMOS Standard Cell-Based Time-to-Digital Converter. In: Chakravarthi, V., Shirur, Y., Prasad, R. (eds) Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013). Lecture Notes in Electrical Engineering, vol 258. Springer, India. https://doi.org/10.1007/978-81-322-1524-0_13
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DOI: https://doi.org/10.1007/978-81-322-1524-0_13
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