Skip to main content
SpringerLink
Log in

Model-Based Representations for Dataflow Schedules

  • Chapter
  • First Online:
Principles of Modeling

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 10760))

Abstract

Dataflow is widely used as a model of computation in many application domains, especially domains within the broad area of signal and information processing. The most common uses of dataflow techniques in these domains are in the modeling of application behavior and the design of specialized architectures. In this chapter, we discuss a different use of dataflow that involves its application as a formal model for scheduling applications onto architectures. Scheduling is a critical aspect of dataflow-based system design that impacts key metrics, including latency, throughput, buffer memory requirements, and energy efficiency. Deriving efficient and reliable schedules is an important and challenging problem that must be addressed in dataflow-based design flows. The concepts and methods reviewed in this chapter help to address this problem through model-based representations of schedules. These representations build on the separation of concerns between functional specification and scheduling in dataflow, and provide a useful new class of abstractions for designing dataflow graph schedules, as well as for managing, analyzing, and manipulating schedules within design tools.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    As compared to being hidden in the C-code of the implementation.

  2. 2.

    This is done so as to ensure that the scheduling network can be calculated easily.

References

  1. Bambha, N., Kianzad, V., Khandelia, M., Bhattacharyya, S.S.: Intermediate representations for design automation of multiprocessor DSP systems. J. Des. Autom. Embed. Syst. 7(4), 307–323 (2002)

    Article  Google Scholar 

  2. Bhattacharyya, S.S., Deprettere, E., Leupers, R., Takala, J. (eds.): Handbook of Signal Processing Systems, 2nd edn. Springer, Heidelberg (2013). https://doi.org/10.1007/978-1-4419-6345-1

    Book  Google Scholar 

  3. Bhattacharyya, S.S., Sriram, S., Lee, E.A.: Optimizing synchronization in multiprocessor DSP systems. IEEE Trans. Signal Process. 45(6), 1605–1618 (1997)

    Article  Google Scholar 

  4. Bhattacharyya, S.S., Eker, J., Janneck, J.W., Lucarz, C., Mattavelli, M., Raulet, M.: Overview of the MPEG reconfigurable video coding framework. J. Signal Process. Syst. 63(2), 251–263 (2009)

    Article  Google Scholar 

  5. Bilsen, G., Engels, M., Lauwereins, R., Peperstraete, J.A.: Cyclo-static dataflow. IEEE Trans. Signal Process. 44(2), 397–408 (1996)

    Article  Google Scholar 

  6. Boutellier, J., Ersfolk, J., Lilius, J., Mattavelli, M., Roquier, G., Silvén, O.: Actor merging for dataflow process networks. IEEE Trans. Signal Process. 63(10), 2496–2508 (2015)

    Article  MathSciNet  Google Scholar 

  7. Buck, J.T., Lee, E.A.: Scheduling dynamic dataflow graphs using the token flow model. In: Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, April 1993

    Google Scholar 

  8. Dahlin, A., Ersfolk, J., Yang, G., Habli, H., Lilius, J.: The canals language and its compiler. In: Proceedings of the 12th International Workshop on Software and Compilers for Embedded Systems SCOPES 2009, pp. 43–52. ACM, New York (2009). http://dl.acm.org/citation.cfm?id=1543820.1543829

  9. Damavandpeyma, M., Stuijk, S., Basten, T., Geilen, M., Corporaal, H.: Modeling static-order schedules in synchronous dataflow graphs. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp. 775–780 (2012)

    Google Scholar 

  10. Desnos, K., Pelcat, M., Nezan, J.F., Aridhi, S.: Distributed memory allocation technique for synchronous dataflow graphs. In: 2016 IEEE International Workshop on Signal Processing Systems (SiPS), pp. 45–50. IEEE (2016)

    Google Scholar 

  11. Ha, S., Teich, J. (eds.): Handbook of Hardware/Software Codesign. Springer, Heidelberg (2017). https://doi.org/10.1007/978-94-017-7267-9

    Book  Google Scholar 

  12. Lee, E.A., Ha, S.: Scheduling strategies for multiprocessor real time DSP. In: Proceedings of the Global Telecommunications Conference, vol. 2, pp. 1279–1283 (1989)

    Google Scholar 

  13. Lee, E.A., Messerschmitt, D.G.: Synchronous dataflow. Proc. IEEE 75(9), 1235–1245 (1987)

    Article  Google Scholar 

  14. Lilius, J., Dahlin, A., Morel, L.: Rialto 2.0: a language for heterogeneous computations. In: Hinchey, M., et al. (eds.) BICC/DIPES -2010. IAICT, vol. 329, pp. 7–18. Springer, Heidelberg (2010). https://doi.org/10.1007/978-3-642-15234-4_3

    Chapter  Google Scholar 

  15. Lin, S., et al.: Parameterized sets of dataflow modes and their application to implementation of cognitive radio systems. J. Signal Process. Syst. 80(1), 3–18 (2015)

    Article  Google Scholar 

  16. Plishker, W., Sane, N., Kiemb, M., Anand, K., Bhattacharyya, S.S.: Functional DIF for rapid prototyping. In: Proceedings of the International Symposium on Rapid System Prototyping, pp. 17–23, Monterey, California, June 2008

    Google Scholar 

  17. Plishker, W., Sane, N., Kiemb, M., Bhattacharyya, S.S.: Heterogeneous design in functional DIF. In: Bereković, M., Dimopoulos, N., Wong, S. (eds.) SAMOS 2008. LNCS, vol. 5114, pp. 157–166. Springer, Heidelberg (2008). https://doi.org/10.1007/978-3-540-70550-5_18

    Chapter  Google Scholar 

  18. Ptolemaeus, C. (ed.): System Design, Modeling, and Simulation using Ptolemy II. Ptolemy.org (2014). http://ptolemy.org/books/Systems

  19. Reiter, R.: Scheduling parallel computations. J. Assoc. Comput. Mach. 15, 590–599 (1968)

    Article  Google Scholar 

  20. Renfors, M., Neuvo, Y.: The maximum sampling rate of digital filters under hardware speed constraints. IEEE Trans. Circ. Syst. 28, 196–202 (1981)

    Article  MathSciNet  Google Scholar 

  21. Sriram, S., Bhattacharyya, S.S.: Embedded Multiprocessors: Scheduling and Synchronization, 2nd edn. CRC Press, Boca Raton (2009). ISBN: 1420048015

    Book  Google Scholar 

  22. Sriram, S., Lee, E.A.: Determining the order of processor transactions in statically scheduled multiprocessors. J. VLSI Signal Process. Syst. Signal Image Video Technol. 15(3), 207–220 (1997)

    Article  Google Scholar 

  23. Stuijk, S., Geilen, M., Basten, T.: Throughput-buffering trade-off exploration for cyclo-static and synchronous dataflow graphs. IEEE Trans. Comput. 57(10), 1331–1345 (2008)

    Article  MathSciNet  Google Scholar 

  24. Wu, H., Shen, C., Sane, N., Plishker, W., Bhattacharyya, S.S.: A model-based schedule representation for heterogeneous mapping of dataflow graphs. In: Proceedings of the International Heterogeneity in Computing Workshop, pp. 66–77, Anchorage, Alaska, May 2011

    Google Scholar 

  25. Zebelein, C., Haubelt, C., Falk, J., Schwarzer, T., Teich, J.: Representing mapping and scheduling decisions within dataflow graphs. In: Proceedings of the Forum on Specification and Design Languages (2013)

    Google Scholar 

Download references

Acknowledgements

This work was supported in part by TEKES—the Finnish Technology Agency for Innovation (FiDiPro project StreamPro 1846/31/2014).

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Maryland, College Park, MD, USA

    Shuvra S. Bhattacharyya

  2. Department of Pervasive Computing, Tampere University of Technology, Tampere, Finland

    Shuvra S. Bhattacharyya

  3. Department of Information Technologies, Åbo Akademi, Åbo, Finland

    Johan Lilius

Authors
  1. Shuvra S. Bhattacharyya
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Johan Lilius
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Shuvra S. Bhattacharyya .

Editor information

Editors and Affiliations

  1. University of California, Berkeley, Berkeley, California, USA

    Marten Lohstroh

  2. National Instruments, Berkeley, California, USA

    Patricia Derler

  3. Mälardalen University, Västerås, Sweden, Reykjavík University, Reykjavik, Iceland

    Marjan Sirjani

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer International Publishing AG, part of Springer Nature

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Bhattacharyya, S.S., Lilius, J. (2018). Model-Based Representations for Dataflow Schedules. In: Lohstroh, M., Derler, P., Sirjani, M. (eds) Principles of Modeling. Lecture Notes in Computer Science(), vol 10760. Springer, Cham. https://doi.org/10.1007/978-3-319-95246-8_6

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-95246-8_6

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-95245-1

  • Online ISBN: 978-3-319-95246-8

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation