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Spiking Neural Network with 256 × 256 PCM Array

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Neuro-inspired Computing Using Resistive Synaptic Devices

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Abstract

Spiking neural network has potential to provide power efficiency and additional functionality compared to conventional artificial neural network (ANN) due to its distinctive features such as spike representation and computation capability using time. The incompatibility of spiking neural network (SNN) to conventional von Neumann computing architecture necessitates development of novel computing architecture for spiking neural network. Neuromorphic computing architecture with nonvolatile memory devices storing synaptic weights can lead to area- and power-efficient hardware implementation for spiking neural network. We will discuss one such neuromorphic chip implementation which has 256 on-chip neuron circuits and 64 k PCM synaptic cells with on-chip learning capability. The two-transistor one-resistor synaptic unit cell structure enables each synaptic cell in the array to operate in asynchronous and parallel fashion, which facilitates scaling up to a larger neural network.

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  1. IBM T. J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, NY, 10598, USA

    SangBum Kim

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Correspondence to SangBum Kim .

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  1. School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, Arizona, USA

    Shimeng Yu

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Kim, S. (2017). Spiking Neural Network with 256 × 256 PCM Array. In: Yu, S. (eds) Neuro-inspired Computing Using Resistive Synaptic Devices. Springer, Cham. https://doi.org/10.1007/978-3-319-54313-0_8

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  • DOI: https://doi.org/10.1007/978-3-319-54313-0_8

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-54312-3

  • Online ISBN: 978-3-319-54313-0

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