Book 2017

Neuro-inspired Computing Using Resistive Synaptic Devices

Editors:

ISBN: 978-3-319-54312-3 (Print) 978-3-319-54313-0 (Online)

Table of contents (14 chapters)

  1. Front Matter

    Pages i-xi

  2. No Access

    Chapter

    Pages 1-15

    Introduction to Neuro-Inspired Computing Using Resistive Synaptic Devices

  3. Device-Level Demonstrations of Resistive Synaptic Devices

    1. Front Matter

      Pages 17-17

    2. No Access

      Chapter

      Pages 19-51

      Synaptic Devices Based on Phase-Change Memory

    3. No Access

      Chapter

      Pages 53-71

      Pr0.7Ca0.3MnO3 (PCMO)-Based Synaptic Devices

    4. No Access

      Chapter

      Pages 73-95

      TaOx-/TiO2-Based Synaptic Devices

  4. Array-Level Demonstrations of Resistive Synaptic Devices and Neural Networks

    1. Front Matter

      Pages 97-97

    2. No Access

      Chapter

      Pages 99-111

      Training and Inference in Hopfield Network Using 10 × 10 Phase Change Synaptic Array

    3. No Access

      Chapter

      Pages 113-134

      Experimental Demonstration of Firing Rate Neural Networks Based on Metal-Oxide Memristive Crossbars

    4. No Access

      Chapter

      Pages 135-151

      Weight Tuning of Resistive Synaptic Devices and Convolution Kernel Operation on 12 × 12 Cross-Point Array

    5. No Access

      Chapter

      Pages 153-164

      Spiking Neural Network with 256 × 256 PCM Array

  5. Circuit, Architecture and Algorithm-Level Design of Resistive Synaptic Devices Based Neuromorphic System

    1. Front Matter

      Pages 165-165

    2. No Access

      Chapter

      Pages 167-182

      Peripheral Circuit Design Considerations of Neuro-inspired Architectures

    3. No Access

      Chapter

      Pages 183-207

      Processing-In-Memory Architecture Design for Accelerating Neuro-Inspired Algorithms

    4. No Access

      Chapter

      Pages 209-231

      Multilayer Perceptron Algorithm: Impact of Nonideal Conductance and Area-Efficient Peripheral Circuits

    5. No Access

      Chapter

      Pages 233-251

      Impact of Nonideal Resistive Synaptic Device Behaviors on Implementation of Sparse Coding Algorithm

    6. No Access

      Chapter

      Pages 253-269

      Binary OxRAM/CBRAM Memories for Efficient Implementations of Embedded Neuromorphic Circuits

  6. Chapter

    Pages E1-E1

    Erratum to: Binary OxRAM/CBRAM Memories for Efficient Implementations of Embedded Neuromorphic Circuits