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Multiple On-Chip Power Supply Systems

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On-Chip Power Delivery and Management

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Abstract

With recent developments in nanometer CMOS technologies, excessive power dissipation has become a limiting factor in integrating a greater number of transistors onto a single monolithic substrate. With the introduction of systems-on-chip, systems-in-package (SiP), and 3-D integrated technologies , the problem of heat removal has further worsened [591–593]. Unless power consumption is dramatically reduced, packaging and performance of ultra large scale integration (ULSI) circuits will become fundamentally limited by heat dissipation.

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Author information

Authors and Affiliations

  1. University of Rochester, Rochester, NY, USA

    Inna P.-Vaisband

  2. Qualcomm Corporation, San Diego, CA, USA

    Renatas Jakushokas

  3. Qualcomm Corporation, San Marcos, CA, USA

    Mikhail Popovich

  4. Intel Corporation, Hillsboro, ON, USA

    Andrey V. Mezhiba

  5. University of South Florida, Tampa, NY, USA

    Selçuk Köse

  6. University of Rochester, Rochester, USA

    Eby G. Friedman

Authors
  1. Inna P.-Vaisband
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  2. Renatas Jakushokas
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  3. Mikhail Popovich
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  4. Andrey V. Mezhiba
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  5. Selçuk Köse
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  6. Eby G. Friedman
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P.-Vaisband, I., Jakushokas, R., Popovich, M., Mezhiba, A.V., Köse, S., Friedman, E.G. (2016). Multiple On-Chip Power Supply Systems. In: On-Chip Power Delivery and Management. Springer, Cham. https://doi.org/10.1007/978-3-319-29395-0_40

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  • DOI: https://doi.org/10.1007/978-3-319-29395-0_40

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-29393-6

  • Online ISBN: 978-3-319-29395-0

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