Power Optimization Based on Link Breaking Methodology

Abstract

A change in voltage at the power node of a gate can significantly increase the delay of a logic gate [32, 498, 499], degrading the overall performance of a system [34]. Since different circuits are affected differently by a drop in the power supply voltage, the power distribution network should be designed to satisfy multiple constraints. The voltage level for those gates along the critical path can tolerate the least voltage degradation, whereas the gates along a noncritical path may satisfy speed constraints despite a higher voltage drop [289]. Circuits, such as a phase-locked loops and voltage controlled oscillators (VCOs), are highly sensitive to changes in the power supply voltage [500]. Alternatively, digital logic circuits can tolerate much higher variations in the power supply voltage. The voltage level of a power distribution network across an entire IC is typically maintained within 10 % degradation, while for a PLL, the voltage level should satisfy a maximum 2 % voltage degradation. To satisfy these constraints, the current supplied to the PLL is filtered by a DC-to-DC converter or a large on-chip decoupling capacitance placed near the PLL [501]. The decoupling capacitors and DC-to-DC converters however consume large area and can dissipate significant power [338].