Abstract
We analyse the external behaviour of parallel delay-insensitive modules in order to formalise the notions of arbitration and reversibility, and investigate universality of classes of such modules. A new notation for parallel modules is developed, where inputs can be sets of signals, which is used to define arbitration and module inversion. We show that arbitrating modules are more expressive than non-arbitrating modules, and propose universal sets for two classes of non-arbitrating modules. We demonstrate previously unrealised constructions of M ×N Join and M ×N Fork in terms of purely reversible and non-arbitrating modules.
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Morrison, D., Ulidowski, I. (2014). Arbitration and Reversibility of Parallel Delay-Insensitive Modules. In: Yamashita, S., Minato, Si. (eds) Reversible Computation. RC 2014. Lecture Notes in Computer Science, vol 8507. Springer, Cham. https://doi.org/10.1007/978-3-319-08494-7_6
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DOI: https://doi.org/10.1007/978-3-319-08494-7_6
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