Skip to main content
SpringerLink
Log in

Conventional Methods for Fault Diagnosis

  • Chapter
  • First Online:
Machine Learning Support for Fault Diagnosis of System-on-Chip

  • 367 Accesses

Abstract

Designers have to be prepared for the scenario where chips do not work as intended or do not meet performance expectations after they are fabricated. Product yield engineers need to know what has caused their product yield to be below expectation. Reliability engineers need to know what circuits or elements have failed from various stresses and those that are returned by the customers. Debug and diagnosis of chip failures is necessary to find the root cause of these issues, and it is best facilitated if the design has accommodated features for debug and diagnosis.

This chapter focuses on the automated tools and methods along with design features at the architectural, logic, circuit, and layout level that are needed to facilitate silicon debug and defect diagnosis of integrated circuits. These design features are generally referred to as design for debug and diagnosis (DFD). We explain how these DFD features along with automated tools and methods are used effectively in a debug or diagnosis environment for applications ranging from design validation, low yield analysis, and all the way to field failure analysis. This chapter will serve as a steppingstone to understand further how conventional methods for fault diagnosis can be improved using machine learning based techniques in subsequent chapters.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 16.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 89.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Similar content being viewed by others

References

  1. Josephson, D., Poehlman, S., Govan, V.: Debug Methodology for the McKinley Processor. In: IEEE International Test Conference, pp. 451–460 (2001, October)

    Google Scholar 

  2. van Rootselaar, G.J., Vermeulen, B.: Silicon Debug: Scan Chains Alone Are Not Enough. In: IEEE International Test Conference, pp. 892–902 (1999, September)

    Google Scholar 

  3. Gizopoulos, D. (ed.): Advances in Electronic Testing: Challenges and Methodologies Series: Frontiers in Electronic Testing. Springer, Boston (2006)

    Google Scholar 

  4. Gangartikar, P., Presson, R., Rosner, L.: Test/Characterization Procedures for High Density Silicon RAMs. In: IEEE International Solid-State Circuits Conference, pp. 62–63 (1982, May)

    Google Scholar 

  5. Hammond, J., Sery, G.: Knowledge-Based Electrical Monitor Approach Using Very Large Array Yield Structures to Delineate Defects During Process Development and Production Yield Improvement. In: Proceedings of International Workshop on Defect and Fault Tolerance in VLSI, pp. 67–80 (1991, November)

    Google Scholar 

  6. Segal, J., Jee, A., Lepejian, D., Chu, B.: Using Electrical Bitmap Results from Embedded Memory to Enhance Yield. In: IEEE Design and Test of Computers, pp. 28–39 (2001, May–June)

    Google Scholar 

  7. Livengood, R.H., Medeiros, D.: Design for (Physical) Debug for Silicon Microsurgery and Probing of Flip-Chip Packaged Integrated Circuits. In: IEEE International Test Conference, pp. 877–882 (1999, September)

    Google Scholar 

  8. Abramovici, M., Breuer, M.A., Friedman, A.D.: Digital Systems Testing and Testable Design. IEEE Press, Revised Printing, Piscataway (1994)

    Google Scholar 

  9. Bushnell, M.L., Agrawal, V.D.: Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits. Springer, Boston (2000)

    Google Scholar 

  10. Jha, N., Gupta, S.: Testing of Digital Systems. Cambridge University Press, London (2003)

    Book  Google Scholar 

  11. Wang, L.-T., Wu, C.-W., Wen, X. (eds.): VLSI Test Principles and Architectures: Design for Testability. Morgan Kaufmann, San Francisco (2006)

    Google Scholar 

  12. Guo, R., Venkataraman, S.: An algorithmic technique for diagnosis of faulty scan chains. IEEE Trans. Comput-Aided Des. 25(9), 1861–1868 (2006)

    Article  Google Scholar 

  13. Venkataraman, S., Drummonds, S.B.: Poirot: Applications of a logic fault diagnosis tool. IEEE Des. Test Comput. 18(1), 19–30 (2001)

    Article  Google Scholar 

  14. Waicukauski, J.A., Lindbloom, E.: Failure diagnosis of structured VLSI. IEEE Des. Test Comput. 6(4), 49–60 (1989)

    Article  Google Scholar 

  15. Eichelberger, E.B., Williams, T.W.: A Logic Design Structure for LSI Testability. In: IEEE Design Automation Conference, pp. 462–468 (1977, June)

    Google Scholar 

  16. Hao, H., Avra, R.: Structured Design for Debug - The SuperSPARC-II Methodology and Implementation. In: IEEE International Test Conference, pp. 175–183 (1995, October)

    Google Scholar 

  17. Carbine, A.: Scan Mechanism for Monitoring the State of Internal Signals of a VLSI Microprocessor Chip. U.S. Patent No. 5,253,255 (1993, October 12)

    Google Scholar 

  18. Carbine, A., Feltham, D.: Pentium Pro Processor Design for Test and Debug. In: IEEE International Test Conference, pp. 294–303 (1997, November)

    Google Scholar 

  19. Sogomonyan, E.S., Morosov, A., Gossel, M., Singh, A., Rzeha, J.: Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed debugging. In: IEEE VLSI Test Symposium, pp. 184–189 (2001, April)

    Google Scholar 

  20. IEEE Std. 1149.1-2001: IEEE Standard Test Access Port and Boundary Scan Architecture. IEEE Press, New York (2001)

    Google Scholar 

  21. Abramovici, M., Bradley, P., Dwarakanath, K., Levin, P., Memmi, G., Miller, D.: A Reconfigurable Design-for-Debug Infrastructure for SoCs. In: ACM/IEEE Design Automation Conference, pp. 2–12 (2006, July)

    Google Scholar 

  22. D. C. Pham, T. Aipperspach, D. Boerstler, M. Bolliger, R. Chaudhry, D. Cox, P. Harvey, P. M. Harvey, H. P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Pham, J. Pille, S. Posluszny, M. Riley, D. L. Stasiak, M. Suzuoki, O. Takahashi, J. Warnock, S. Weitzel, D. Wendel, and K. Yazawa, “Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor,” IEEE J. Solid-State Circuits, Vol. 41, No. 1, pp. 179–196, Jan. 2006.

    Google Scholar 

  23. Kurd, N.A., Barkarullah, J.S., Dizon, R.O., Fletcher, T.D., Madland, P.D.: A Multigigahertz clocking scheme for the Pentium 4 microprocessor. IEEE J Solid State Circuits. 36(11), 1647–1653 (2001)

    Article  Google Scholar 

  24. Fetzer, E.S.: Using adaptive circuits to mitigate process variations in a microprocessor design. IEEE Des. Test Comput. 23(6), 476–483 (2006)

    Article  Google Scholar 

  25. Josephson, D., Gottlieb, B.: The Crazy Mixed up World of Silicon Debug [IC validation]. In: IEEE Custom Integrated Circuits Conference, pp. 665–670 (2004, October)

    Google Scholar 

  26. Mahoney, P., Fetzer, E., Doyle, B., Naffziger, S.: Clock Distribution on a Dual-Core, Multi-Threaded Itanium Family Processor. In: Digest of Papers, IEEE International Solid-State Circuits Conference, pp. 292–599, (2005, February)

    Google Scholar 

  27. Aitken, R.C.: Finding Defects with Fault Models. In: IEEE International Test Conference, pp. 498–505 (1995, October)

    Google Scholar 

  28. Venkataraman, S., Drummonds, S.B.: A Technique for Logic Fault Diagnosis of Interconnect Open Defects. In: IEEE VTS, pp. 313–318 (2000)

    Google Scholar 

  29. Chang, Y.-J., et al.: Experiences with Layout-Aware Diagnosis. In: Electronic Device Failure Analysis (2010, May)

    Google Scholar 

  30. Mekkoth, J., et al.: Yield Learning with Layout-aware Advanced Scan Diagnosis. In: International Symposium of Testing and Failure Analysis (ISTFA) (2006)

    Google Scholar 

  31. Amyeen, M.E., Nayak, D., Venkataraman, S.: Improving Precision Using Mixed-level Fault Diagnosis, IEEE International Test Conference (2006), Paper: 22.3

    Google Scholar 

  32. Tendolkar, N., et al.: Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. In: ITC (2006)

    Google Scholar 

  33. Gearhardt, K., Schuermyer, C., Guo, R.: Improving Fault Isolation using Iterative Diagnosis. In: 34th International Symposium for Failure Analysis, pp. 390–391 (2008, November 2–6)

    Google Scholar 

  34. Cheng, W.-T., Tsai, K.-H., Huang, Y., Tamarapalli, N., Rajski, J.: Compactor Independent Direct Diagnosis. In: Proceedings of Asian Test Symposium, pp. 15–17 (2004)

    Google Scholar 

  35. Stanojevic, Z., Guo, R., Mitra, S., Venkataraman, S.: Enabling Yield Analysis with X-compact. In: IEEE International Test Conference, pp. 734–742 (2005)

    Google Scholar 

  36. Cheng, W.-T., Sharma, M., Rinderknecht, T., Liyang, L., Hill, C.: Signature based diagnosis for logic BIST. In: IEEE International Test Conference (2007, October 21–26)

    Google Scholar 

  37. Burmer, C., Guo, R., Cheng, W.-T., Lin, X., Benware, B.: Timing Failure Debug using Debug-Friendly Scan Patterns and TRE. In: 34th International Symposium for Failure Analysis, pp. 383–389 (2008, November 2–6)

    Google Scholar 

  38. Sharma, M., Cheng, W.-T., Tai, T.-P., Cheng, Y.S., Hsu, W., Chen, L., Reddy, S.M., Mann, A.: Faster Defect Localization in Nanometer Technology Based on Defective Cell Diagnosis. In: IEEE International Test Conference (2007, October 21–26)

    Google Scholar 

  39. Fan, X., Moore, W., Hora, C., Gronthoud, G.: A Novel Stuck-at Based Method for Transistor Stuck-Open Fault Diagnosis. In: IEEE International Test Conference, pp. 253–262 (2005)

    Google Scholar 

  40. Fan, X., Moore, W., Hora, C., Konijnenburg, M., Gronthoud, G.: A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis. In: Proceedings of the IEEE VLSI Test Symposium (2006)

    Google Scholar 

  41. Basturkmen, N.Z., Guo, R., Venkataraman, S.: Diagnosis of Multiple Scan Chain Failures. In: Proceedings of European Test Symposium (2008)

    Google Scholar 

  42. Lee, K.L., Basturkmen, N.Z., Venkataraman, S.: Diagnosis of Scan Clock Failures. In: Proceedings of VLSI Test Symposium, pp. 67–72 (2008)

    Google Scholar 

  43. Tang, X., Guo, R., Cheng, W.-T., Reddy, S.M., Huang, Y.: On Improving Diagnostic Test Generation for Scan Chain Failures. In: Asian Test Symposium (2009)

    Google Scholar 

  44. Wang, F., Hu, Y., Li, H., Li, X., Jing, Y., Huang, Y.: Diagnostic Pattern Generation for Compound Defects. In: ITC (2008), paper 14.1

    Google Scholar 

  45. Huang, Q., Fang, C., Mittal, S., Blanton, R.D.: Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer. ACM Trans. Des. Automat. Electron. Syst. - Special Issue on Machine Learning 25(5), 1–20 (2020)

    Google Scholar 

  46. Xue, Y., Poku, O., Li, X., Blanton, R.D.: PADRE: Physically-Aware Diagnostic Resolution Enhancement. In: IEEE International Test Conference, pp. 1–10 (2013)

    Google Scholar 

  47. Xue, Y., Li, X., Blanton, R.D.: Improving diagnostic resolution of failing ICs through learning. IEEE Trans. Comput-Aided Des. Integr. Circuits Syst. 37(6), 1288–1297 (2018)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Intel Corporation, Hillsboro, OR, USA

    Srikanth Venkat Raman

Authors
  1. Srikanth Venkat Raman
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Srikanth Venkat Raman .

Editor information

Editors and Affiliations

  1. LIRMM - CNRS, Montpellier, France

    Patrick Girard

  2. Carnegie Mellon University, Pittsburgh, PA, USA

    Shawn Blanton

  3. University of California, Santa Barbara, Santa Barbara, CA, USA

    Li-C. Wang

Rights and permissions

Reprints and permissions

Copyright information

© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Venkat Raman, S. (2023). Conventional Methods for Fault Diagnosis. In: Girard, P., Blanton, S., Wang, LC. (eds) Machine Learning Support for Fault Diagnosis of System-on-Chip . Springer, Cham. https://doi.org/10.1007/978-3-031-19639-3_2

Download citation

  • DOI: https://doi.org/10.1007/978-3-031-19639-3_2

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-19638-6

  • Online ISBN: 978-3-031-19639-3

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation