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Machine Learning in Alternate Testing of Integrated Circuits

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Machine Learning Paradigms

Part of the book series: Learning and Analytics in Intelligent Systems ((LAIS,volume 1))

Abstract

Integrated circuit (IC) fabrication involves sophisticated and sensitive equipment, while design complexity and scale of integration are increasing in order to obtain the largest functionality within the smallest possible chip area. As ICs scale down, increasing uncertainties in the manufacturing processes lead to increased numbers of malfunctioning chips that have to be detected and withdrawn early in the production stage in order to assure product quality. Testing an IC for compliance with its specifications might require a considerable amount of time and resources, since a wide range of different tests—each tailored for a specific performance characteristic—should be performed, resulting in the collection of extremely large data sets that correspond to test data. In order to reduce test time and cost, several machine learning techniques have been applied for the identification of patterns and non-linear correlations among test data and performance characteristics. Furthermore, data analytics have achieved promising results in areas such as test quality prediction and fault diagnosis. In this chapter, the Alternate Test paradigm is presented since it is probably the most well-established machine learning application in the field of IC testing. Alternate Test is performed by the exploitation of a set of common test observables—produced using simple stimuli and cost-effective equipment of low complexity—that are sufficiently correlated to all performance characteristics of interest. Following the supervised learning approach, non-linear regression models are constructed for each performance characteristic, that provide accurate performance predictions based on the values of the measured test observables. Using statistical feature selection techniques, a low dimensionality can be obtained for the set of test observables, by which a further reduction in test time and cost can be achieved.

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Author information

Authors and Affiliations

  1. Department of Computer Engineering, Technological Educational Institute of Peloponnese, Kladas, Valiotis Building, 23100, Sparta, Greece

    John Liaperdos

  2. Department of Informatics and Telecommunications, National and Kapodistrian University of Athens, Panepistimiopolis, Ilissia, 15784, Athens, Greece

    Angela Arapoyanni

  3. Department of Computer Science and Engineering, University of Ioannina, Panepistimioupolis, 45110, Ioannina, Greece

    Yiorgos Tsiatouhas

Authors
  1. John Liaperdos
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  2. Angela Arapoyanni
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  3. Yiorgos Tsiatouhas
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Corresponding author

Correspondence to John Liaperdos .

Editor information

Editors and Affiliations

  1. University of Piraeus, Pireas, Greece

    George A. Tsihrintzis

  2. Department of Informatics, University of Piraeus, Piraeus, Greece

    Maria Virvou

  3. University of Piraeus, Piraeus, Greece

    Evangelos Sakkopoulos

  4. Faculty of Engineering and Information Technology, Centre for Artificial Intelligence, University of Technology Sydney, NSW, Australia

    Lakhmi C. Jain

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Liaperdos, J., Arapoyanni, A., Tsiatouhas, Y. (2019). Machine Learning in Alternate Testing of Integrated Circuits. In: Tsihrintzis, G., Virvou, M., Sakkopoulos, E., Jain, L. (eds) Machine Learning Paradigms. Learning and Analytics in Intelligent Systems, vol 1. Springer, Cham. https://doi.org/10.1007/978-3-030-15628-2_16

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