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Wet Chemical Processes for BEOL Technology

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Springer Handbook of Semiconductor Devices

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Abstract

This chapter covers wet processes for logic back-end-of-the-line interconnect technology – namely, wet cleans and wet etching (Sect. 6.1), electroplating (Sect. 6.2), and chemical mechanical planarization (Sect. 6.3). Each section details the introduction of the process and equipment used in 300-mm semiconductor industry from the beginning of Cu era. All the critical components of the process and equipment are described followed by the experimental results and discussion for each of the application. In wet cleans and wet etching section, applications like post-etch residue clean, backside clean, and hardmask wet etch are covered. Plating section includes copper electroplating of damascene and dual damascene structures. In chemical mechanical planarization section, metal – copper, tantalum, tantalum nitride, and cobalt – polishing and planarization, and post-cleaning applications are covered.

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Authors and Affiliations

  1. IBM, Albany, NY, USA

    Cornelius Brown Peethala, James J. Kelly & Donald F. Canaperi

  2. IBM Research, Albany, NY, USA

    Takeshi Nogami

  3. IBM, Yorktown Heights, NY, USA

    Mahadevaiyer Krishnan

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Peethala, C.B., Kelly, J.J., Canaperi, D.F., Krishnan, M., Nogami, T. (2023). Wet Chemical Processes for BEOL Technology. In: Rudan, M., Brunetti, R., Reggiani, S. (eds) Springer Handbook of Semiconductor Devices . Springer Handbooks. Springer, Cham. https://doi.org/10.1007/978-3-030-79827-7_6

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