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Mapping Conductance and Carrier Distributions in Confined Three-Dimensional Transistor Structures

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Electrical Atomic Force Microscopy for Nanoelectronics

Part of the book series: NanoScience and Technology ((NANO))

Abstract

Probing the distribution of charge carriers in semiconductor device structures is of crucial importance to better understand semiconductor fabrication processes and how they affect the incorporation, diffusion and activation of dopants and hence the final device performance. Scanning spreading resistance microscopy (SSRM) has emerged as the most valuable technique for 2D and 3D carrier mapping in semiconductor device structures due to its excellent spatial resolution, sensitivity and ease of quantification. The present chapter first introduces the principles of the technique, thereby discussing the underlying physical mechanisms such as the nanometer-size probe-semiconductor contact. Faced with the stringent requirements imposed by advanced 3D device architectures, novel approaches and concepts such as 3D carrier profiling and fast Fourier transform-SSRM (FFT-SSRM) have been developed in the recent years. These methods aid in extending conventional SSRM toward quantitative carrier profiling in aggressively scaled 3D device structures which is illustrated on the example of selected relevant applications such as FinFETs and nanowire-based transistors.

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Acknowledgements

The authors acknowledge C. Drijbooms, P. Favia and H. Bender for their contributions related to FIB and TEM work.

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Author notes

  1. Andreas Schulze

    Present address: Applied Materials, 3340 Scott Boulevard, Santa Clara, CA, 95054, USA

  2. Jay Mody

    Present address: Globalfoundries, 400 Stone Break Rd Extension, Malta, 12020, USA

Authors and Affiliations

  1. IMEC, Kapeldreef 75, 3001, Leuven, Belgium

    Andreas Schulze, Pierre Eyben, Kristof Paredis, Lennaert Wouters, Umberto Celano & Wilfried Vandervorst

  2. Department of Physics and Astronomy, KU Leuven, 3001, Leuven, Belgium

    Wilfried Vandervorst

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Schulze, A. et al. (2019). Mapping Conductance and Carrier Distributions in Confined Three-Dimensional Transistor Structures. In: Celano, U. (eds) Electrical Atomic Force Microscopy for Nanoelectronics. NanoScience and Technology. Springer, Cham. https://doi.org/10.1007/978-3-030-15612-1_3

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