Abstract
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. Especially software controlled loop buffers are energy efficient. However current compilers do not fully take advantage of the possibilities of such loop buffers. This paper presents an algorithm the explore for an application or a set of applications what is the optimal loop buffer configuration and the optimal way to use this configuration. Results for the MediaBench application suite show an additional 35% reduction (on average) in energy in the instruction memory hierarchy as compared to traditional approaches to the loop buffer without any performance implications.
This project is partially supported by the Fund for Scientific Research – Flanders (FWO) through projects G.0036.99 and G.0160.02 and the postdoctoral fellowship of G.Deconinck, and by the IWT through MEDEA+ project A502 MESA.
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References
Anderson, T., Agarwala, S.: Effective hardware-based two-way loop cache for high performance low power processors. In: Proc of ICCD (September 2000)
Bajwa, R.S., et al.: Instruction buffering to reduce power in processors for signal processing. IEEE Transactions on VLSI 5(4), 417–424 (1997)
Bellas, N., Hajj, I., Polychronopoulos, C., Stamoulis, G.: Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors. In: Proc of ISLPED (August 1998)
Benini, L., Bruni, D., Chinosi, M., Silvano, C., Zaccaria, V., Zafalon, R.: A power modeling and estimation framework for vliw-based embedded systems. In: Proc. Int. Workshop on Power And Timing Modeling, Optimization and Simulation PATMOS (September 2001)
Benini, L., de Micheli, G.: Sysmtem-level power optimization: Techniques and tools. ACM TODAES 5(2), 115–192 (2000)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework for architectural-level power analysis and optimizations. In: Proc of ISCA, pp. 83–94 (June 2000)
Catthoor, F., Danckaert, K., Kulkarni, C., Brockmeyer, E., Kjeldsberg, P.G., Van Achteren, T., Omnes, T.: Data access and storage management for embedded programmable processors. Kluwer Academic Publishers, Dordrecht (2002)
Cotterell, S., Vahid, F.: Tuning of loop cache architectures to programs in embedded system design. In: Proc of International Symposium on System Synthesis (ISSS) (October 2002)
Gordon-Ross, A., Cotterell, S., Vahid, F.: Exploiting fixed programs in embedded systems: A loop cache example. In: Proc of IEEE Computer Architecture Letters (January 2002)
Jacome, M.F., de Veciana, G.: Design challenges for new application-specific processors. Special issue on Design of Embedded Systems in IEEE Design & Test of Computers (April-June 2000)
Jayapala, M., Barat, F., OpDe Beeck, P., Catthoor, F., Deconinck, G., Corporaal, H.: A low energy clustered instruction memory hierarchy for long instruction word processors. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds.) PATMOS 2002. LNCS, vol. 2451, p. 258. Springer, Heidelberg (2002)
Kin, J., Gupta, M., Mangione-Smith, W.H.: Filtering memory references to increase energy efficiency. IEEE Transactions on Computers 49(1), 1–15 (2000)
Lee, C., et al.: Mediabench: A tool for evaluating and synthesizing multimedia and communicatons systems. In: International Symposium on Microarchitecture, pp. 330–335 (1997)
Lee, L.H., Moyer, B., Arends, J., Arbor, A.: Low-cost embedded program loop caching - revisited. Technical report, EECS, University of Michigan (December 1999)
Lee, L.H., Moyer, W., Arends, J.: Instruction fetch energy reduction using loop caches for embedded applications with small tight loops. In: Proc of ISLPED (August 1999)
Panda, P.R., Dutt, N.D., Nicolau, A.: Memory data organization for improved cache performance in embedded processor applications. ACM TODAES 2(4), 384–409 (1997)
Slavenburg, G.A., Rathnam, S., Dijkstra, H.: The Trimedia TM-1 PCI VLIW media processor. In: Proceedings Hot Chips VIII Conference (1996)
Texas Instruments Inc., TMS320 DSP Family Overview, http://www.ti.com
Trimaran group. Trimaran: An Infrastructure for Research in Instruction-Level Parallelism (1999), http://www.trimaran.org
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Vander Aa, T. et al. (2003). Instruction Buffering Exploration for Low Energy Embedded Processors. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_47
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DOI: https://doi.org/10.1007/978-3-540-39762-5_47
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