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Analysis and Design of Networks-on-Chip Under High Process Variation

  • Book
  • © 2015

Overview

  • Demonstrates the impact of process variation on Networks-on-Chip
  • of different topologies
  • Includes an overview of the synchronous clocking scheme, clock
  • distribution network, main building blocks in asynchronous NoC design,
  • handshake protocols, data encoding, asynchronous protocol converters and
  • routing algorithms
  • Describes a novel adaptive routing algorithm for asynchronous NoC designs, which selects the appropriate output path based on process variation and congestion
  • Includes supplementary material: sn.pub/extras

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Table of contents (8 chapters)

  1. Background

  2. Impact of Process Variation on Low and High Levels Designs

  3. Simulation Results and Future Work

Keywords

About this book

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.


Authors and Affiliations

  • Electrical Engineering Department, Beni-Suef University, Bani Sweif, Egypt

    Rabab Ezz-Eldin

  • Electronics Research Institute, Cairo, Egypt

    Magdy Ali El-Moursy

  • Electrical Engineering Department, Minia University, Minya, Egypt

    Hesham F. A. Hamed

About the authors

Magdy Ali El-Moursy is an Associate Professor in the Microelectronics Department of the Electronics Research Institute, Cairo, Egypt and Staff Engineer at Design Creation and Synthesis Division of Mentor Graphics Corporation, Cairo, Egypt.

Bibliographic Information

  • Book Title: Analysis and Design of Networks-on-Chip Under High Process Variation

  • Authors: Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed

  • DOI: https://doi.org/10.1007/978-3-319-25766-2

  • Publisher: Springer Cham

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer International Publishing Switzerland 2015

  • Hardcover ISBN: 978-3-319-25764-8Published: 23 December 2015

  • Softcover ISBN: 978-3-319-79837-0Published: 23 March 2019

  • eBook ISBN: 978-3-319-25766-2Published: 16 December 2015

  • Edition Number: 1

  • Number of Pages: XXI, 141

  • Number of Illustrations: 50 b/w illustrations, 34 illustrations in colour

  • Topics: Circuits and Systems, Processor Architectures, Electronics and Microelectronics, Instrumentation

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