Guest Editors'; Introduction Keshab K. ParhiTakao NishitaniHironori Yamauchi Legacy 01 May 1997 Pages: 5 - 7
A Low-Power Encoder For Pyramid Vector Quantization of Subband Coefficients Won NamgoongTeresa H. Meng OriginalPaper 01 May 1997 Pages: 9 - 23
A Single-Chip MPEG/Audio Decoder LSI Based on a Compact Decoding Algorithm Masahiro IwadareHideto TakanoNaoko Kobayashi OriginalPaper 01 May 1997 Pages: 25 - 30
An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor Johannes KneipMladen BerekovicPeter Pirsch OriginalPaper 01 May 1997 Pages: 31 - 40
Architectural Synthesis of Digital Signal Processing Algorithms Using “IRIS” D.W. TrainorR.F. WoodsJ.V. McCanny OriginalPaper 01 May 1997 Pages: 41 - 55
A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis Kazuhito ItoKeshab K. Parhi OriginalPaper 01 May 1997 Pages: 57 - 72
Compiled Simulation of Programmable DSP Architectures Vojin ZivojnovićSteven TjiangHeinrich Meyr OriginalPaper 01 May 1997 Pages: 73 - 80
Efficient Implementation Methodology of Fast FIR Filtering Algorithms on DSP Anissa ZergaïnohPierre DuhamelJean Pierre Vidal OriginalPaper 01 May 1997 Pages: 81 - 103