1. Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder

   • Yu-Han Chen
   • Tung-Chien Chen
   • Liang-Gee Chen

   OriginalPaper 16 August 2007 Pages: 1 - 17

2. A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC

   • Yu Li
   • Yun He
   • Shunliang Mei

   OriginalPaper 04 October 2007 Pages: 19 - 32

3. Architecture Considerations for Multi-Format Programmable Video Processors

   • Jonah Probell

   OriginalPaper 24 July 2007 Pages: 33 - 39

4. A Novel Cost-Effective and Programmable VLSI Architecture of CAVLC Decoder for H.264/AVC

   • Yanmei Qu
   • Yun He
   • Shunliang Mei

   OriginalPaper 04 October 2007 Pages: 41 - 51

5. ASIP Approach for Implementation of H.264/AVC

   • Sung Dae Kim
   • Myung H. Sunwoo

   OriginalPaper 16 August 2007 Pages: 53 - 67

6. Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead

   • Tsu-Ming Liu
   • Chen-Yi Lee

   OriginalPaper 16 August 2007 Pages: 69 - 80

7. A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC

   • Lingfeng Li
   • Yang Song
   • Satoshi Goto

   OriginalPaper 16 August 2007 Pages: 81 - 95