Volume 31, Issue 6 | International Journal of Parallel Programming

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Volume 31, Issue 6

December 2003

Workshop on Application Specific Processors (WASP)

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6 articles in this issue

Guest Editor's Introduction
Alex Orailoglu
Introduction Pages: 407 - 409
Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints
Kubilay Atasu
Laura Pozzi
Paolo Ienne
OriginalPaper Pages: 411 - 428
Automatic Design of Application Specific Instruction Set Extensions Through Dataflow Graph Exploration
Nathan Clark
Hongtao Zhong
Scott Mahlke
OriginalPaper Pages: 429 - 449
Power-Aware Compilation for Register File Energy Reduction
José L. Ayala
Alexander Veidenbaum
Marisa López-Vallejo
OriginalPaper Pages: 451 - 467
On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications
G. Surendra
S. Banerjee
S. K. Nandy
OriginalPaper Pages: 469 - 487
A Reconfigurable Logic-Based Processor for the SCAN Image and Video Encryption Algorithm
C. Kachris
N. Bourbakis
A. Dollas
OriginalPaper Pages: 489 - 506